parameters from floating point registers if target is mips64 hard float.

llvm-svn: 176520

llvm-svn: 176519

llvm-svn: 176518

- resolved circular dependency issue by making liblldb depend directly on LLDBWrapPython.cpp
- removed use of '..' for relative directories -- ninja doesn't like this
- fixed build-order problem

llvm-svn: 176517

llvm-svn: 176516

llvm-svn: 176515

This patch adds many more functions to the target library information.
All of the functions being added were discovered while doing the migration
of the simplify-libcalls attribute annotation functionality to the
functionattrs pass.  As a part of that work the attribute annotation logic
will query TLI to determine if a function should be annotated or not.

Signed-off-by: Meador Inge <meadori@codesourcery.com>
llvm-svn: 176514

llvm-svn: 176513

field to be memcpy'd, rather instead of ASTContext::getTypeAlign(<Field Type>).
For packed structs the alignment of a field may be less than the alignment of
the field's type.

<rdar://problem/13338585>

llvm-svn: 176512

llvm-svn: 176511

llvm-svn: 176510

checkings and few other refactoring/cleanup.
// rdar://13094352.

llvm-svn: 176509

llvm-svn: 176508

llvm-svn: 176507

'R' An address that can be sued in a non-macro load or store.

Including missing positive test case and fixed typo for r176453.

Thanks to Richard Smith for catching this!

Jack

llvm-svn: 176506

llvm-svn: 176505

llvm-svn: 176504

llvm-svn: 176503

Patch by David Sehr

llvm-svn: 176502

llvm-svn: 176501

llvm-svn: 176500

Set imMoveImm, isAsCheapAsAMove flags for TFRI instructions.

llvm-svn: 176499

This is a skeleton for a pre-RA MachineInstr scheduler strategy. Currently
it only tries to expose more parallelism for ALU instructions (this also
makes the distribution of GPR channels more uniform and increases the
chances of ALU instructions to be packed together in a single VLIW group).
Also it tries to reduce clause switching by grouping instruction of the
same kind (ALU/FETCH/CF) together.

Vincent Lejeune:
 - Support for VLIW4 Slot assignement
 - Recomputation of ScheduleDAG to get more parallelism opportunities

Tom Stellard:
 - Fix assertion failure when trying to determine an instruction's slot
   based on its destination register's class
 - Fix some compiler warnings

Vincent Lejeune: [v2]
 - Remove recomputation of ScheduleDAG (will be provided in a later patch)
 - Improve estimation of an ALU clause size so that heuristic does not emit cf
 instructions at the wrong position.
 - Make schedule heuristic smarter using SUnit Depth
 - Take constant read limitations into account

Vincent Lejeune: [v3]
 - Fix some uninitialized values in ConstPair
 - Add asserts to ensure an ALU slot is always populated

llvm-svn: 176498

llvm-svn: 176497

llvm-svn: 176494

Fixed code to match text. Slight adjustment for readability.

Author: Béatrice Creusillet
llvm-svn: 176493

llvm-svn: 176492

Clarify that we mean the object starting at the pointer to the end of the
underlying object and not the size of the whole allocated object.

llvm-svn: 176491

llvm-svn: 176490

[ELF] Set symbol type to STT_SECTION, so that objdump.bfd doesnot get confused when disassembling output

llvm-svn: 176489

Maintaining CONST_COPY Instructions until Pre Emit may prevent some ifcvt case
and taking them in account for scheduling is difficult for no real benefit.

llvm-svn: 176488

Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
llvm-svn: 176487

Reviewed-by: Tom Stellard <thomas.stellard at amd.com>

mayLoad complexify scheduling and does not bring any usefull info
as the location is not writeable at all.

llvm-svn: 176486

Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
llvm-svn: 176485

NOTE: This is a candidate for the Mesa stable branch.
llvm-svn: 176484

llvm-svn: 176483

llvm-svn: 176482

Print a warning message if compiler-rt can't be built because of old CMake version to make this requirement more visible to users

llvm-svn: 176481

llvm-svn: 176480

llvm-svn: 176479