Part of rdar://11352000

llvm-svn: 156405

I still left another fixme regarding alignment, because I'm unsure how to remove that code without breaking things

llvm-svn: 156387

remove TYPE_CODE_FUNCTION_OLD type code. it is no longer in use and it was marked for removal in 3.0

llvm-svn: 156383

Share the CalleeSavedRegs defs between all calling conventions having no
callee-saved registers.

Patch by Yiannis Tsiouris!

llvm-svn: 156382

Files might be opend by system scanners (eg. file indexer, virus scanner, &c).

llvm-svn: 156380

replace the operands of expressions with only one use with undef and generate
a new expression for the original without using RAUW to update the original.
Thus any copies of the original expression held in a vector may end up
referring to some bogus value - and using a ValueHandle won't help since there
is no RAUW.  There is already a mechanism for getting the effect of recursion
non-recursively: adding the value to be recursed on to RedoInsts.  But it wasn't
being used systematically.  Have various places where recursion had snuck in at
some point use the RedoInsts mechanism instead.  Fixes PR12169.

llvm-svn: 156379

llvm-svn: 156377

llvm-svn: 156375

Added new case-ranges orientated methods for adding/removing cases in SwitchInst. After this patch cases will internally representated as ConstantArray-s instead of ConstantInt, externally cases wrapped within the ConstantRangesSet object.
Old methods of SwitchInst are also works well, but marked as deprecated. So on this stage we have no side effects except that I added support for case ranges in BitcodeReader/Writer, of course test for Bitcode is also added. Old "switch" format is also supported.

llvm-svn: 156374

llvm-svn: 156358

No functional change.

llvm-svn: 156345

llvm-svn: 156342

At least some of them:

  %vreg1:sub_16bit = COPY %vreg2:sub_16bit; GR64:%vreg1, GR32: %vreg2

Previously, we couldn't figure out that the above copy could be
eliminated by coalescing %vreg2 with %vreg1:sub_32bit.

The new getCommonSuperRegClass() hook makes it possible.

This is not very useful yet since the unmodified part of the destination
register usually interferes with the source register. The coalescer
needs to understand sub-register interference checking first.

llvm-svn: 156334

The getPointerRegClass() hook can return register classes that depend on
the calling convention of the current function (ptr_rc_tailcall).

So far, we have been able to infer the calling convention from the
subtarget alone, but as we add support for multiple calling conventions
per target, that no longer works.

Patch by Yiannis Tsiouris!

llvm-svn: 156328

Test cases for this code are coming. It is not used for anything yet.

llvm-svn: 156327

llvm-svn: 156324

Teach reassociate to commute FMul's and FAdd's in order to canonicalize the order of their operands across instructions.  This allows for greater CSE opportunities.

llvm-svn: 156323

optional library support to the llvm-build tool:
 - Add new command line parameter to llvm-build: “--enable-optional-libraries”
 - Add handing of new llvm-build library type “OptionalLibrary”
 - Update Cmake and automake build systems to pass correct flags to llvm-build
   based on configuration

Patch by Dan Malea!

llvm-svn: 156319

This function is a generalization of getMatchingSuperRegClass() to the
symmetric case where both sides are using a sub-register index. It will
find a super-register class and sub-register indexes that make this
diagram commute:

                                   PreA
                       SuperRC  ---------->  RCA

                          |                   |
                          |                   |
                     PreB |                   | SubA
                          |                   |
                          |                   |
                          V                   V

                         RCB    ----------> SubRC
                                   SubB

This can be used to coalesce copies like:

  %vreg1:sub16 = COPY %vreg2:sub16; GR64:%vreg1, GR32: %vreg2

llvm-svn: 156317

single use.
rdar://11360370

llvm-svn: 156316

Fixes a -Woverflow warning from gcc when building for 32-bit platforms.

llvm-svn: 156313

This patch will optimize -(x != 0) on X86
FROM 
cmpl	$0x01,%edi
sbbl	%eax,%eax
notl	%eax
TO
negl %edi
sbbl %eax %eax

In order to generate negl, I added patterns in Target/X86/X86InstrCompiler.td:
def : Pat<(X86sub_flag 0, GR32:$src), (NEG32r GR32:$src)>;

rdar: 10961709
llvm-svn: 156312

Patch by Jack Carter.

llvm-svn: 156295

Patch by Jack Carter.

llvm-svn: 156294

Patch by Jack Carter.

llvm-svn: 156293

Patch by Jack Carter.

llvm-svn: 156292

llvm-svn: 156287

Patch by Jack Carter.

llvm-svn: 156285

Patch by Jack Carter.

llvm-svn: 156284

Patch by Jack Carter.

llvm-svn: 156283

llvm-svn: 156282

llvm-svn: 156281

Patch by Jack Carter.

llvm-svn: 156280

from the previous 2 patches.

Patch by Jack Carter.

llvm-svn: 156279

Patch by Jack Carter.

llvm-svn: 156278

non-floating point general registers allow 8 and 16-bit
elements.

Patch by Jack Carter.

llvm-svn: 156277

Use MVT instead of EVT as the argument to all the shuffle decode functions. Simplify some of the decode functions.

llvm-svn: 156268

Add VPERMQ/VPERMPD to the list of target specific shuffles that can be looked through for DAG combine purposes.

llvm-svn: 156266

llvm-svn: 156265

llvm-svn: 156260