Add vvvv support to disassembling of instructions with MRMDestMem and MRMDestReg form. Needed to support mem dest form of vmaskmovps/d. Fixes PR10807.

llvm-svn: 138795

llvm-svn: 138780

llvm-svn: 138779

llvm-svn: 138778

llvm-svn: 138777

llvm-svn: 138773

llvm-svn: 138771

llvm-svn: 138754

Add support for parsing #-0 on non-memory-operand immediate values, and add a testcase that necessitates it.

llvm-svn: 138739

Improve encoding support for BLX with immediat eoperands, and fix a BLX decoding bug this uncovered.

llvm-svn: 138675

llvm-svn: 138673

invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons.  We were failing to specify enough fixed bits of LDR_PRE/LDRB_PRE, resulting in decoding conflicts.  Separate them into immediate vs. register versions, allowing us to specify the necessary fixed bits.  This in turn results in the test being decoded properly, and being rejected as UNPREDICTABLE rather than a hard failure.

llvm-svn: 138653

Support an extension of ARM asm syntax to allow immediate operands to ADR instructions.  This is helpful for disassembler testing, and indeed exposed a disassembler bug that is also fixed here.

llvm-svn: 138635

llvm-svn: 138626

llvm-svn: 138623

Port over additional encoding tests to decoding tests, and fix an operand ordering bug this exposed.

llvm-svn: 138575

Give ATTR_VEX higher priority when generating the disassembler context table. Fixes disassembling of VEX instructions with 'pp'=00. Fixes subset of PR10678.

llvm-svn: 138552

Add TB encoding to VEROALL, VZEROUPPER, and VCVTPS2PD to allow them to be disassembled. Fixes PR10723.

llvm-svn: 138551

.cfi_startproc. e.g. libffi:

 $ cat confopt.c 
asm (".cfi_startproc\n\t.cfi_endproc");

int main () { return 0; }

Teach MC / dwarf emission to handle these cfi directives which essentially
create an empty frame.

rdar://10017184

llvm-svn: 138504

llvm-svn: 138502

Fix FiXME in test file. Remove FIXME for SUB (SP minus register) since that
form is Thumb2 only.

llvm-svn: 138494

Fix the test FIXME and add parsing support for the ADD (SP plus immediate)
and ADD (SP plus register) instruction forms.

llvm-svn: 138488

llvm-svn: 138441

llvm-svn: 138364

llvm-svn: 138363

llvm-svn: 138362

llvm-svn: 138361

llvm-svn: 138360

llvm-svn: 138359

llvm-svn: 138352

llvm-svn: 138349

llvm-svn: 138348

Not including tSTRspi.

llvm-svn: 138347

llvm-svn: 138345

Fix decoding of Thumb2 prefetch instructions, which account for all the remaining Thumb2 decoding failures found by randomized testing so far.

llvm-svn: 138341

Fix two more instances of mis-matched operand names breaking disassembly.  Found by randomized testing.

llvm-svn: 138337

llvm-svn: 138336

llvm-svn: 138312

llvm-svn: 138311

llvm-svn: 138308