[analyzer] Remove references to idx::TranslationUnit. Index is dead, cross-TU inlining never panned out.

llvm-svn: 155751

disallowing reads over 1KiB in total size
unless the user explicitly allows them.

llvm-svn: 155750

This time, also fix the caller of AddGlue to properly handle
incomplete chains. AddGlue had failure modes, but shamefully hid them
from its caller. It's luck ran out.

Fixes rdar://11314175: BuildSchedUnits assert.

llvm-svn: 155749

Make sure when parsing the Thumb1 sp+register ADD instruction that
the source and destination operands match. In thumb2, just use the
wide encoding if they don't. In Thumb1, issue a diagnostic.

rdar://11219154

llvm-svn: 155748

Make the operand order of the instruction match that of the asm syntax.

llvm-svn: 155747

llvm-svn: 155746

On x86-32, structure return via sret lets the callee pop the hidden
pointer argument off the stack, which the caller then re-pushes.
However if the calling convention is fastcc, then a register is used
instead, and the caller should not adjust the stack. This is
implemented with a check of IsTailCallConvention
X86TargetLowering::LowerCall but is now checked properly in
X86FastISel::DoSelectCall.

llvm-svn: 155745

Previously, ARMConstantIslandPass would conservatively compute the
address of an aligned basic block as:

  RoundUpToAlignment(Offset + UnknownPadding)

This worked fine for the layout algorithm itself, but it could fool the
verify() function because it accounts for alignment padding twice: Once
when adding the worst case UnknownPadding, and again by rounding up the
fictional block offset. This meant that when optimizeThumb2Instructions
would shrink an instruction, the conservative distance estimate could
grow. That shouldn't be possible since the woorst case alignment padding
wss already included.

This patch drops the use of RoundUpToAlignment, and depends only on
worst case padding to compute conservative block offsets. This has the
weird effect that the computed offset for an aligned block may not be
aligned.

The important difference is that shrinking an instruction can never
cause the estimated distance between two instructions to grow. The
estimated distance is always larger than the real distance that only the
assembler knows.

<rdar://problem/11339352>

llvm-svn: 155744

This definitely caused regression with ARM -mno-thumb.

llvm-svn: 155743

llvm-svn: 155742

llvm-svn: 155741

nonfragile ivar access code when ivar type is a 
locally defined struct/union type. // rdar://11323187

llvm-svn: 155740

 x == -y --> x+y == 0
 x != -y --> x+y != 0

On x86, the generated code goes from
   negl    %esi
   cmpl    %esi, %edi
   je    .LBB0_2
to
   addl    %esi, %edi
   je    .L4

This case is correctly handled for ARM with "cmn".

Patch by Manman Ren.
rdar://11245199
PR12545

llvm-svn: 155739

up with gaps when the class inherits from the same empty base class
more than once. Fixes <rdar://problem/11324167>.

llvm-svn: 155738

The Avida Project (http://avida.devosoft.org) exceeds the 256 limit.
rdar://11289131

llvm-svn: 155737

symbols should be static. // rdar://11337074

llvm-svn: 155736

llvm-svn: 155735

llvm-svn: 155733

llvm-svn: 155732

architecture; this was happening for tools such as lipo and dsymutil.
Also, if no -arch option has been specified, set the architecture based
on the TC default.
rdar://11329656

llvm-svn: 155730

Target specific types should not be vectorized. As a practical matter,
these types are already register matched (at least in the x86 case),
and codegen does not always work correctly (at least in the ppc case,
and this is not worth fixing because ppc_fp128 is currently broken and
will probably go away soon).

llvm-svn: 155729

We do not support IRGen for these, and get some parts of the semantic analysis
wrong.

llvm-svn: 155728

llvm-svn: 155727

llvm-svn: 155726

llvm-svn: 155725

<rdar://problem/11325085>.

llvm-svn: 155724

llvm-svn: 155723

The limit is set to an arbitrary 1000 recursion depth to avoid stack overflow
issues. <rdar://problem/11286839>.

llvm-svn: 155722

properly with how the code handles all-undef PHI nodes.

llvm-svn: 155721

llvm-svn: 155720

intended.

llvm-svn: 155719

intended.

llvm-svn: 155718

This is an incomplete implementation of the SCEV based code generation.
When finished it will remove the need for -indvars -enable-iv-rewrite.

For the moment it is still disabled. Even though it passes 'make polly-test',
there are still loose ends especially in respect of OpenMP code generation.

llvm-svn: 155717

llvm-svn: 155716

llvm-svn: 155708

llvm-svn: 155706

llvm-svn: 155705

* Model FPSW (the FPU status word) as a register.
* Add ISel patterns for the FUCOM*, FNSTSW and SAHF instructions.
* During Legalize/Lowering, build a node sequence to transfer the comparison
result from FPSW into EFLAGS. If you're wondering about the right-shift: That's
an implicit sub-register extraction (%ax -> %ah) which is handled later on by
the instruction selector.

Fixes PR6679. Patch by Christoph Erhardt!

llvm-svn: 155704

This change replaces projects/sample/autoconf/config.sub with a copy of
autoconf/config.sub.

llvm-svn: 155703

llvm-svn: 155701