llvm-svn: 101638

llvm-svn: 101637

llvm-svn: 101636

const_casts, and it reinforces the design of the Target classes being
immutable.

SelectionDAGISel::IsLegalToFold is now a static member function, because
PIC16 uses it in an unconventional way. There is more room for API
cleanup here.

And PIC16's AsmPrinter no longer uses TargetLowering.

llvm-svn: 101635

MachineFunctionInfo subclasses.

llvm-svn: 101634

Also rename the classes appropriately. The CMake build already used these
names.

llvm-svn: 101631

i8 field when they really do not.  This fixes rdar://7840289

llvm-svn: 101629

CGSCC can delete nodes in regions of the callgraph that
have already been visited.  If new CG nodes are allocated
to the same pointer, we shouldn't abort, just handle it
correctly by assigning a new number.  This should restore
stability by removing invalidated pointers that *will* be
reused from the densemap in the iterator.

llvm-svn: 101628

the live-in sets of BBs in the loop. Otherwise later pass may end up using the
registers and override the invariant. rdar://7852937
No reasonablly sized test case possible.

llvm-svn: 101626

llvm-svn: 101622

llvm-svn: 101621

llvm-svn: 101620

may be called when either the source or destination type is i64, and my
change also hadn't fixed the most obvious problem -- assuming that i64 will
only be bitconverted to f64, ignoring the various vector types.
Radar 7873160.

llvm-svn: 101615

to determine where to place PHIs by iteratively comparing reaching definitions
at each block.  That was just plain wrong.  This version now computes the
dominator tree within the subset of the CFG where PHIs may need to be placed,
and then places the PHIs in the iterated dominance frontier of each definition.
The rest of the patch is mostly the same, with a few more performance
improvements added in.

llvm-svn: 101612

just remove them all.  Radar 7873207 (working around the root problem of
Radar 7759363).

llvm-svn: 101604

Revert "Use a simpler data structure to calculate the least recently used register in RegAllocLocal."

This reverts commit 101392. It broke a buildbot.

llvm-svn: 101595

llvm-svn: 101583

llvm-svn: 101581

Probably the best way to know that all getOperand() calls have been handled
is to replace that API instead of updating.

llvm-svn: 101579

llvm-svn: 101575

This makes the local register allocator about 20% faster.

llvm-svn: 101574

llvm-svn: 101573

to keep the node entries in scc_iterator up to date instead of dangling as
the SCC mutates.

This is a really terrible problem which was causing -g to affect codegen 
because it would permute the memory image of the compiler process.

Thanks to Dale for expertly hunting it down.

llvm-svn: 101565

llvm-svn: 101564

on it.

llvm-svn: 101563

No functionality change.

llvm-svn: 101562

to CallGraphSCCPass's instead of passing around a
std::vector<CallGraphNode*>.  No functionality change,
but now we have a much tidier interface.

llvm-svn: 101558

case.  Also, the 0xFF hex literal involved in the shift for ESize64 should be
suffixed "ul" to preserve the shift result.

Implemented printHex*ImmOperand() by copying from ARMAsmPrinter.cpp and added a
test case for DisassembleN1RegModImmFrm()/printHex64ImmOperand().

llvm-svn: 101557

(i32 sext_in_reg (i32 aext (i16 x)), i16) -> (i32 sext x). No known test case until -promote-16bit is enabled.

llvm-svn: 101551

llvm-svn: 101543

llvm-svn: 101538

SelectionDAG-specific parts of TargetLowering.

llvm-svn: 101537

llvm-svn: 101532

llvm-svn: 101531

this patch removes the assert() from printAddrMode3OffsetOperand() and adds a test case.

llvm-svn: 101529

to the UAL syntax of LDCL<c>, instead.

Add a test case for this change which also tests the removal of assert() from
printAddrMode2OffsetOperand().

llvm-svn: 101527

considered legal instructions.

Refs: A8.6.51 LDC, LDC2 (immediate) -- page A8-107, A8.6.58 LDR (immediate, ARM)
-- page A8-121, and A8.6.194 STR (immediate, ARM) -- page A8-395.

llvm-svn: 101524

llvm-svn: 101501

llvm-svn: 101500

llvm-svn: 101480