of just letting them inherit the debug locations of adjacent instructions.

Debug info should aim to be either accurate or absent.

llvm-svn: 103135

llvm-svn: 103134

llvm-svn: 103133

llvm-svn: 103129

that was causing PC-relative branch targets to be
evaluated incorrectly.  Also added support for
checking operand values to the llvm-mc tester.

llvm-svn: 103128

llvm-svn: 103126

a magic project name.

llvm-svn: 103125

Do not pre-allocate references of D registers pairs if they are extracted from the same Q register and are in the right order.

llvm-svn: 103124

llvm-svn: 103122

user's source, so don't arbitrarily assign them a debug location.

llvm-svn: 103121

llvm-svn: 103120

Jordy <snhjordy@gmail.com>.

Followup patches will add some tests and adjust to use Subtarget features
for the instructions.

llvm-svn: 103119

This fixes the compile-time regressions seen in last night's tests.

llvm-svn: 103118

llvm-svn: 103114

llvm-svn: 103113

writing them.
 - <rdar://problem/7885351> integrated assembler broken for i386 objc code

llvm-svn: 103112

llvm-svn: 103111

llvm-svn: 103110

llvm-svn: 103109

Microoptimize Twine's with unsigned and int to not pin their value to
the stack.  This saves stack space in common cases and allows mem2reg
in the caller.  A simple example is:

void foo(const Twine &);
void bar(int x) {
  foo("xyz: " + Twine(x));
}

Before:

__Z3bari:
	subq	$40, %rsp
	movl	%edi, 36(%rsp)
	leaq	L_.str3(%rip), %rax
	leaq	36(%rsp), %rcx
	leaq	8(%rsp), %rdi
	movq	%rax, 8(%rsp)
	movq	%rcx, 16(%rsp)
	movb	$3, 24(%rsp)
	movb	$7, 25(%rsp)
	callq	__Z3fooRKN4llvm5TwineE
	addq	$40, %rsp
	ret

After:

__Z3bari:
	subq	$24, %rsp
	leaq	L_.str3(%rip), %rax
	movq	%rax, (%rsp)
	movslq	%edi, %rax
	movq	%rax, 8(%rsp)
	movb	$3, 16(%rsp)
	movb	$7, 17(%rsp)
	leaq	(%rsp), %rdi
	callq	__Z3fooRKN4llvm5TwineE
	addq	$24, %rsp
	ret

It saves 16 bytes of stack and one instruction in this case.

llvm-svn: 103107

ddunbar says the gcc-4.3.3 suppressions are obsolete.

llvm-svn: 103106

llvm-svn: 103104

llvm-svn: 103103

Teach liveintervalanalysis about virtual registers which are defined by reg_sequence instructions that are formed by registers defined by distinct instructions. e.g.
80      %reg1041:6<def> = VSHRNv4i16 %reg1034<kill>, 12, pred:14, pred:%reg0
. . .
120     %reg1041:5<def> = VSHRNv4i16 %reg1039<kill>, 12, pred:14, pred:%reg0

llvm-svn: 103102

llvm-svn: 103100

llvm-svn: 103095

when possible.
 - <rdar://problem/7934873>

llvm-svn: 103092

llvm-svn: 103091

This should fix mysteriously crashing boost regression tests when stderr is
managed by bjam (PR7043).

llvm-svn: 103085

when building llvm with clang

llvm-svn: 103084

hack the code to turn it off when debugging.

llvm-svn: 103083

llvm-svn: 103073

llvm-svn: 103071

MachineSSAUpdater to avoid duplicating all the code.

llvm-svn: 103060

llvm-svn: 103057

and diagnostic groups.  This allows the compiler to group 
diagnostics together (e.g. "Logic Warning", 
"Format String Warning", etc) like the static analyzer does.  
This is not exposed through anything in the compiler yet.

llvm-svn: 103050

With -neon-reg-sequence, models forming a Q register from a pair of consecutive D registers as a REG_SEQUENCE.

llvm-svn: 103047

llvm-svn: 103041

Teach PHI elimination to remove REG_SEQUENCE instructions and update references of the source operands with references of the destination with subreg indices. e.g.
%reg1029<def>, %reg1030<def> = VLD1q16 %reg1024<kill>, ...
%reg1031<def> = REG_SEQUENCE %reg1029<kill>, 5, %reg1030<kill>, 6
=>
%reg1031:5<def>, %reg1031:6<def> = VLD1q16 %reg1024<kill>, ...

PHI elimination now does more than phi elimination. It is really a de-SSA pass.

llvm-svn: 103039

values passed to llvm.dbg.value were not valid for the intrinsic, it
might have caused trouble one day if the verifier ever started checking
for valid debug info.

llvm-svn: 103038