llvm-svn: 174412

llvm-svn: 174411

llvm-svn: 174410

llvm-svn: 174409

llvm-svn: 174408

llvm-svn: 174407

llvm-svn: 174406

llvm-svn: 174402

Something very strange is going on with the output registers in this
target. Its ISelLowering code is inserting dangling CopyToReg nodes,
hoping that those physregs won't get clobbered before the RETURN.

This patch adds the output registers as implicit uses on RETURN
instructions in the custom emission pass. I'd much prefer to have those
CopyToReg nodes glued to the RETURNs, but I don't see how.

llvm-svn: 174400

The liveout lists are about to be removed from MRI, this is the only
place they were used after register allocation.

Get the live out V registers directly from the return instructions
instead.

llvm-svn: 174399

Patch by: Vincent Lejeune

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 174395

Use one intrinsic for all sorts of interpolation.
Use two separate unexpanded instructions to represent INTERP_XY and _ZW -
this will allow to eliminate one part if it's not used.
Track liveness of special interpolation regs instead of reserving them -
this will allow to reuse those regs, lowering reg pressure.

Patch By: Vadim Girlin

v2[Vincent Lejeune]: Rebased against current llvm master

Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 174394

Emitting the function name allows us to check for it in the FileCheck
tests so we can make sure FileCheck is checking the output of the
correct function.

llvm-svn: 174392

Fixes 37 piglit tests and allows e.g. FlightGear to run with radeonsi.

Patch by: Michel Dänzer

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 174391

llvm-svn: 174390

for the existing instructions.

llvm-svn: 174389

llvm-svn: 174387

This should fix the valgrind buildbot failure.

llvm-svn: 174375

Also adds some costs for vector integer float conversions.

llvm-svn: 174371

This should fix three purely whitespace issues:
    + 80 column violations.
    + Tab characters.
    + TableGen brace placement.

No functional changes.

llvm-svn: 174370

This moves the bit twiddling and string fiddling functions required by other
parts of the backend into a separate library. Previously they resided in
AArch64Desc, which created a circular dependency between various components.

llvm-svn: 174369

MicroMips architectures. 

Contributer: Zoran Jovanovic
 
llvm-svn: 174360

and enables the instruction printer to print aliased 
instructions. 

Due to usage of RegisterOperands a change in common 
code (utils/TableGen/AsmWriterEmitter.cpp) is required 
to get the correct register value if it is a RegisterOperand.

Contributer: Vladimir Medic
 
llvm-svn: 174358

for MipsELFStreamer objects.

Contributer: Jack Carter
 
llvm-svn: 174354

llvm-svn: 174331

I didn't see those because the test case used "not grep". FileCheck the test and
XFAIL it, preserving the old optimization, so this can be fixed eventually.

llvm-svn: 174330

We were taking a StringRef to a temporary result, which can go horribly wrong.

llvm-svn: 174328

Fixes PR15141.

llvm-svn: 174327

llvm-svn: 174326

This required disabling a PowerPC optimization that did the following:
input:
x = BUILD_VECTOR <i32 16, i32 16, i32 16, i32 16>
lowered to:
tmp = BUILD_VECTOR <i32 8, i32 8, i32 8, i32 8>
x = ADD tmp, tmp

The add now gets folded immediately and we're back at the BUILD_VECTOR we
started from. I don't see a way to fix this currently so I left it disabled
for now.

Fix some trivially foldable X86 tests too.

llvm-svn: 174325

llvm-svn: 174324

This change lets us bootstrap LLVM/Clang under ASan and MSan. It contains
fixes for 2 issues:

- X86JIT reads return address from stack, which MSan does not know is
  initialized.
- bugpoint tests run binaries with RLIMIT_AS. This does not work with certain
  Sanitizers.

We are no longer including config.h in Compiler.h with this change.

llvm-svn: 174306

Swift has a renaming dependency if we load into D subregisters. We don't have a
way of distinguishing between insertelement operations of values from loads and
other values. Therefore, we are pessimistic for now (The performance problem
showed up in example 14 of gcc-loops).

radar://13096933

llvm-svn: 174300

llvm-svn: 174298

llvm-svn: 174297

This checkin makes hello world work. 

llvm-svn: 174264

llvm-svn: 174232

llvm-svn: 174230

1) allows the use of RIP-relative addressing in 32-bit LEA instructions under
   x86-64 (ILP32 and LP64)
2) separates the size of address registers in 64-bit LEA instructions from
   control by ILP32/LP64.

llvm-svn: 174208

llvm-svn: 174193