[SparcV9] Use correct register class (I64RegClass) to hold the address of  _GLOBAL_OFFSET_TABLE_ in sparcv9.

llvm-svn: 200368

llvm-svn: 199033

[Sparc] Add support for parsing jmpl instruction and make indirect call and jmp instructions as aliases to jmpl.

llvm-svn: 198909

llvm-svn: 198893

llvm-svn: 198738

llvm-svn: 198658

llvm-svn: 198591

llvm-svn: 198533

llvm-svn: 198484

llvm-svn: 198286

[SparcV9]: Use SRL instead of SLL to clear top 32-bits in ctpop:i32. SLL does not clear top 32 bit, only SRL does.

llvm-svn: 198280

[SparcV9] Use separate instruction patterns for 64 bit arithmetic instructions instead of reusing 32 bit instruction patterns.
 This is done to avoid spilling the result of the 64-bit instructions to a 4-byte slot.

llvm-svn: 198157

llvm-svn: 195575

llvm-svn: 193957

No new testcases. However, this patch makes all supported JIT testcases in 
test/ExecutionEngine  pass on Sparc.

llvm-svn: 192176

[Sparc] Do not hardcode nop in the delay slot of TLS_CALL. Use DelaySlotFiller to fill the delay slot instead.

llvm-svn: 192160

llvm-svn: 192056

addx/subx does not modify conditional codes whereas addxcc/subxx does.

llvm-svn: 192053

llvm-svn: 191180

[Sparc] Make SPARC instructions' encoding well defined such that TableGen can automatically generate code emitter.

llvm-svn: 191168

[Sparc] Clean up MOVcc instructions so that TableGen can encode them correctly. No functionality change intended.

llvm-svn: 191167

[Sparc] Clean up branch instructions, so that TableGen can encode branch conditions as well. No functionality change intended.

llvm-svn: 191166

llvm-svn: 191164

llvm-svn: 189780

llvm-svn: 189198

llvm-svn: 189085

[Sparc] Use HWEncoding instead of unused Num field in Sparc register definitions. Also, correct the definitions of RETL and RET instructions.

llvm-svn: 188738

llvm-svn: 183613

llvm-svn: 183463

llvm-svn: 183243

llvm-svn: 183094

       using two instructions (sethi and store).

llvm-svn: 183090

Also clean up the arguments to all the MOVCC instructions so the
operands always are (true-val, false-val, cond-code).

llvm-svn: 182221

llvm-svn: 182216

Don't ignore the high 32 bits of the immediate.

llvm-svn: 179985

This fixes the pic32 code model for SPARC v9.

llvm-svn: 179469

This requires v9 cmov instructions using the %xcc flags instead of the
%icc flags.

Still missing:
- Select floats on %xcc flags.
- Select i64 on %fcc flags.

llvm-svn: 178737

The same compare instruction is used for 32-bit and 64-bit compares. It
sets two different sets of flags: icc and xcc.

This patch adds a conditional branch instruction using the xcc flags for
64-bit compares.

llvm-svn: 178621

SPARC v9 defines new 64-bit shift instructions. The 32-bit shift right
instructions are still usable as zero and sign extensions.

This adds new F3_Sr and F3_Si instruction formats that probably should
be used for the 32-bit shifts as well. They don't really encode an
simm13 field.

llvm-svn: 178525

The 'sparc' architecture produces 32-bit code while 'sparcv9' produces
64-bit code.

It is also possible to run 32-bit code using SPARC v9 instructions with:

  llc -march=sparc -mattr=+v9

llvm-svn: 178524