- Aug 28, 2009
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Daniel Dunbar authored
llvm-svn: 80338
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Evan Cheng authored
llvm-svn: 80322
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- Aug 27, 2009
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Anton Korobeynikov authored
scalar_to_vector is fully legal now llvm-svn: 80251
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Anton Korobeynikov authored
llvm-svn: 80250
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Anton Korobeynikov authored
No idea whether this is profitable or not. llvm-svn: 80245
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Misha Brukman authored
See http://llvm.org/PR4687 for more info and links. llvm-svn: 80244
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Evan Cheng authored
Fix PR4789. Teach eliminateFrameIndex how to handle VLDRQ and VSTRQ which cannot fold any immediate offset. llvm-svn: 80191
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- Aug 26, 2009
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Bob Wilson authored
The instructions can be selected directly from the intrinsics. We will need to add some ARM-specific nodes for VLD/VST of 3 and 4 128-bit vectors, but those are not yet implemented. llvm-svn: 80117
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Anton Korobeynikov authored
llvm-svn: 80107
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- Aug 25, 2009
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Bob Wilson authored
llvm-svn: 80015
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Bob Wilson authored
llvm-svn: 80011
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- Aug 24, 2009
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Dale Johannesen authored
all Darwin targets; could be split into separate tests for the chip subdirectories, but from Chris' last mail on testing I assume he'd rather have only one test. Generic seems to be the best available, maybe there should be a Darwin subdirectory? llvm-svn: 79877
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Chris Lattner authored
llvm-svn: 79873
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- Aug 23, 2009
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Benjamin Kramer authored
llvm-svn: 79853
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Chris Lattner authored
llvm-svn: 79833
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Chris Lattner authored
MachineInstr and MachineOperand. This required eliminating a bunch of stuff that was using DOUT, I hope that bill doesn't mind me stealing his fun. ;-) llvm-svn: 79813
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Benjamin Kramer authored
llvm-svn: 79780
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- Aug 22, 2009
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Chris Lattner authored
llvm-svn: 79777
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Chris Lattner authored
llvm-svn: 79773
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Chris Lattner authored
llvm-svn: 79763
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Devang Patel authored
llvm-svn: 79742
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Eli Friedman authored
construct on ARM, which was breaking by coincidence, and add a similar testcase for ARM. llvm-svn: 79719
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- Aug 21, 2009
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Bob Wilson authored
several things other than Neon vector lane numbers. For inline assembly operands with a "c" print code, check that they really are immediates. llvm-svn: 79676
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Bob Wilson authored
now using shuffles instead of intrinsics. llvm-svn: 79673
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Anton Korobeynikov authored
llvm-svn: 79625
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Anton Korobeynikov authored
llvm-svn: 79624
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Anton Korobeynikov authored
llvm-svn: 79622
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Anton Korobeynikov authored
llvm-svn: 79621
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Anton Korobeynikov authored
llvm-svn: 79620
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Anton Korobeynikov authored
Use masks not nodes for vector shuffle predicates. Provide set of 'legal' masks, so legalizer won't infinite cycle llvm-svn: 79619
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Bob Wilson authored
vector shuffles. Temporarily remove the tests for these operations until the new implementation is working. llvm-svn: 79579
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- Aug 20, 2009
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Evan Cheng authored
llvm-svn: 79535
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- Aug 19, 2009
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David Goodwin authored
llvm-svn: 79436
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Bob Wilson authored
This is derived from a patch by Anton Korzh. I modified it to recognize the VEXT shuffles during legalization and lower them to a target-specific DAG node. llvm-svn: 79428
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Chris Lattner authored
talk to the MCStreamer directly instead. llvm-svn: 79405
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- Aug 18, 2009
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Jakob Stoklund Olesen authored
- Drop the Candidates argument and fix all callers. Now that RegScavenger tracks available registers accurately, there is no need to restict the search. - Make sure that no aliases of the found register are in use. This was a potential bug. llvm-svn: 79369
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Evan Cheng authored
llvm-svn: 79318
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- Aug 16, 2009
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Benjamin Kramer authored
llvm-svn: 79189
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- Aug 15, 2009
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Bill Wendling authored
llvm-svn: 79136
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Bill Wendling authored
llvm-svn: 79135
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