This fixes recent regression in store.exp from gdb testsuite.

llvm-svn: 104524

llvm-svn: 104518

never used.

llvm-svn: 104517

Anton, please review the change to SystemZAsmPrinter.cpp. It could be a bug.

llvm-svn: 104515

llvm-svn: 104514

llvm-svn: 104513

Add assertions in places that depend on consecutive indices.

llvm-svn: 104510

from ARMRegisterInfo.h

llvm-svn: 104508

Use the tablegen-produced enums.

llvm-svn: 104493

This is the beginning of purely symbolic subregister indices, but we need a bit
of jiggling before the explicit numeric indices can be completely removed.

llvm-svn: 104492

is first emitted, and StackOffsets are emitted in 16 bits.

llvm-svn: 104488

llvm-mc: Use EmitIntValue where possible, which makes the API calls from the AsmParser and CodeGen line up better.

llvm-svn: 104467

llvm-mc: Use AddBlankLine in asm parser. This makes transliteration match the input much more closely, and also makes the API calls from the AsmParser and CodeGen line up better.

llvm-svn: 104466

llvm-svn: 104463

llvm-svn: 104455

MC/X86: Subdivide immediates a bit more, so that we properly recognize immediates based on the width of the target instruction. For example:
  addw $0xFFFF, %ax
should match the same as
  addw $-1, %ax
but we used to match it to the longer encoding.

llvm-svn: 104453

llvm-svn: 104452

llvm-svn: 104435

llvm-svn: 104421

Followups: docs patch for the builtin and eh.sjlj.setjmp cleanup to match
longjmp.

llvm-svn: 104419

copying VFP subregs.  This exposed a bunch of dead code in the *spill-q.ll
tests, so I tweaked those tests to keep that code from being optimized away.
Radar 7872877.

llvm-svn: 104415

llvm-svn: 104414

llvm-svn: 104412

llvm-svn: 104410

Evan please verify!

llvm-svn: 104408

llvm-svn: 104404

llvm-svn: 104396

llvm-svn: 104394

Allow machine cse to cse instructions which define physical registers. Controlled by option -machine-cse-phys-defs.

llvm-svn: 104385

llvm-svn: 104381

so that it will continue to test what it was meant to test when I commit a
separate change for better support of BUILD_VECTOR and VECTOR_SHUFFLE for Neon.
Fix a DAG combiner crash exposed by this test change.

llvm-svn: 104380

that are aliases of the specified register.
- Rename modifiesRegister to definesRegister since it's looking a def of the
specific register or one of its super-registers. It's not looking for def of a
sub-register or alias that could change the specified register.
- Added modifiesRegister to look for defs of aliases.

llvm-svn: 104377

reads or writes a register.

This takes partial redefines and undef uses into account.

Don't actually use it yet. That caused miscompiles.

llvm-svn: 104372

llvm-svn: 104338

llvm-svn: 104337

Case where MMX is disabled wasn't handled right.
MMX->MMX bitconverts are Legal.

llvm-svn: 104336

pass after isel instead of being interlaced with it, we can
trust that all the code for a function has been isel'd before
it is run.

The practical impact of this is that we can scan for machine
instr phis instead of doing a fuzzy match on the LLVM BB for
phi nodes.  Doing the fuzzy match required knowing when isel
would produce an fp reg stack phi which was gross.  It was
also wrong in cases where select got lowered to a branch
tree because cmovs aren't available (PR6828).

Just do the scan on machine phis which is simpler, faster
and more correct.  This fixes PR6828.

llvm-svn: 104333

llvm-svn: 104331

llvm-svn: 104330

eliminating the gymnastics around the ContainsFPCode var.

llvm-svn: 104328