llvm-svn: 117997

handling those cases for now.

llvm-svn: 117996

llvm-svn: 117995

to what someone would need to do to support thumb1.

llvm-svn: 117994

since we can neither generate nor parse them at the moment.

llvm-svn: 117988

llvm-svn: 117986

llvm-svn: 117984

for handling the fixup necessary.

llvm-svn: 117978

llvm-svn: 117977

This is another part of the fix for Radar 8599955.

llvm-svn: 117976

llvm-svn: 117971

llvm-svn: 117969

llvm-svn: 117964

llvm-svn: 117956

at more than those which define CPSR. You can have this situation:

(1)  subs  ...
(2)  sub   r6, r5, r4
(3)  movge ...
(4)  cmp   r6, 0
(5)  movge ...

We cannot convert (2) to "subs" because (3) is using the CPSR set by
(1). There's an analogous situation here:

(1)  sub   r1, r2, r3
(2)  sub   r4, r5, r6
(3)  cmp   r4, ...
(5)  movge ...
(6)  cmp   r1, ...
(7)  movge ...

We cannot convert (1) to "subs" because of the intervening use of CPSR.

llvm-svn: 117950

llvm-svn: 117940

llvm-svn: 117936

codegen using the patterns; the latter gates the assembler recognizing the
instruction.

llvm-svn: 117931

llvm-svn: 117929

llvm-svn: 117927

patterns as such

llvm-svn: 117923

*_Encode classes. These instructions are the only ones which use those classes,
so a subclass isn't necessary.

llvm-svn: 117906

various X86 and ARM instructions that are bitten by this as isCodeGenOnly,
as they are.

llvm-svn: 117884

Use this to make the X86 and ARM targets set isCodeGenOnly=1 
automatically for their instructions that have Format=Pseudo,
resolving a hack in tblgen.

llvm-svn: 117862

and make it a hard error for instructions to not have an asm string.
These instructions should be marked isCodeGenOnly.

llvm-svn: 117861

got a dulicated line).

llvm-svn: 117860

llvm-svn: 117859

Instead of silently ignoring these instructions, emit a hard error and
force the target author to either refactor the target or mark the 
instruction 'isCodeGenOnly'.

Mark a few instructions in ARM and MBlaze as isCodeGenOnly the are 
doing this.

llvm-svn: 117858

llvm-svn: 117848

llvm-svn: 117787

llvm-svn: 117782

llvm-svn: 117771

llvm-svn: 117769

llvm-svn: 117766

There were a number of issues to fix up here:
* The "device" argument of the llvm.memory.barrier intrinsic should be
used to distinguish the "Full System" domain from the "Inner Shareable"
domain.  It has nothing to do with using DMB vs. DSB instructions.
* The compiler should never need to emit DSB instructions.  Remove the
ARMISD::SYNCBARRIER node and also remove the instruction patterns for DSB.
* Merge the separate DMB/DSB instructions for options only used for the
disassembler with the default DMB/DSB instructions.  Add the default
"full system" option ARM_MB::SY to the ARM_MB::MemBOpt enum.
* Add a separate ARMISD::MEMBARRIER_MCR node for subtargets that implement
a data memory barrier using the MCR instruction.
* Fix up encodings for these instructions (except MCR).
I also updated the tests and added a few new ones to check for DMB options
that were not currently being exercised.

llvm-svn: 117756

llvm-svn: 117753

conditional. Check for those instructions explicitly.

llvm-svn: 117747

llvm-svn: 117742

llvm-svn: 117741

llvm-svn: 117740