Original commit message:
Support/FileSystem: Implement canonicalize.

llvm-svn: 146378

llvm-svn: 146377

Order constant pool entries by descending alignment in the initial
island to ensure packing and correct alignment.  When the command line
flag is set, also align the basic block containing the constant pool
entries.

This is only a partial implementation of constant island alignment. More
to come.

llvm-svn: 146375

a function to upgrade. Also, simplify the code a bit at the expense of
one line.

llvm-svn: 146368

llvm-svn: 146364

llvm-svn: 146363

llvm-svn: 146362

argument of the cttz and ctlz intrinsics.

llvm-svn: 146360

indicates whether the intrinsic has a defined result for a first
argument equal to zero. This will eventually allow these intrinsics to
accurately model the semantics of GCC's __builtin_ctz and __builtin_clz
and the X86 instructions (prior to AVX) which implement them.

This patch merely sets the stage by extending the signature of these
intrinsics and establishing auto-upgrade logic so that the old spelling
still works both in IR and in bitcode. The upgrade logic preserves the
existing (inefficient) semantics. This patch should not change any
behavior. CodeGen isn't updated because it can use the existing
semantics regardless of the flag's value.

Note that this will be followed by API updates to Clang and DragonEgg.

Reviewed by Nick Lewycky!

llvm-svn: 146357

The OptLevel is now redundant with the TargetMachine*.
And selectTarget() isn't really JIT-specific and could probably
get refactored into one of the lower level libraries.

llvm-svn: 146355

Remove some remants of the old palign pattern fragment that were still hanging around. Also remove a cast from inside getShuffleVPERM2X128Immediate and getShuffleVPERMILPImmediate since the only caller already had done the cast.

llvm-svn: 146344

Fixed bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2). Third attempt: simplified checks in test for armv7-apple-darwin11.

llvm-svn: 146341

llvm-svn: 146340

of r146334!

llvm-svn: 146338

llvm-svn: 146335

the only parts of TM that depends on CodeGen headers with it.

llvm-svn: 146334

[fast-isel] SelectInsertValue seems to be causing miscompiles for ARM.  Disable while I investigate.

llvm-svn: 146331

Fixed bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for
FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2). Second
attempt.

llvm-svn: 146328

llvm-svn: 146327

Fixed bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2). Second attempt.

llvm-svn: 146322

Make CR spill and restore use a reserved register. These operations cannot use the register scavenger because the scavenger can only scavenge one register and frame-index elimination may have already grabbed it.

llvm-svn: 146318

The split point is picked such that the newly created water has the same
alignment as the function. This makes the island suitable for constant
pool entries with potentially higher alignment.

This also fixes an issue where the basic block was split one instruction
too late, causing nonconvergence of the algorithm.

<rdar://problem/10550705>

There is still an issue with correctly packing differently aligned
entries in the island.

llvm-svn: 146314

llvm-svn: 146313

does. The _GLOBAL_OFFSET_TABLE_ is still magical in that we get a R_386_GOTPC,
but it doesn't change the immediate in the same way as when the expression
has no right hand side symbol.

llvm-svn: 146311

Since we're not rewriting IVs in other loops, there's not much reason
to consider their stride when generating formulae.
This should reduce the number of useless formulas considered by LSR.

llvm-svn: 146302

llvm-svn: 146300

llvm-svn: 146299

llvm-svn: 146296

llvm-svn: 146293

Backwards compatibility with 'gas'. #imm is the preferered and documented
syntax, but lots of existing code uses the '$' prefix, so we should
support it if we can.

llvm-svn: 146285

[asan] call __asan_init from .preinit_array. This simplifies __asan_init vs malloc chicken-and-egg situation on Android and probably on other flavours of Linux. Patch by eugenis@google.com.

llvm-svn: 146284

When the immediate operand of an AND or BIC instruction isn't representable
in the immediate field of the instruction, but the bitwise negation of the
immediate is, assemble the instruction as the inverse operation instead
with the inverted immediate as the operand.

rdar://10550057

llvm-svn: 146283

llvm-svn: 146281

Refactor the instructions into fixed writeback and register-stride
writeback variants to simplify the offset operand (no more optional
register operand using reg0). This is a simpler representation and allows
the assembly parser to more easily handle these instructions.

Add tests for the instruction variants now supported.

llvm-svn: 146278

llvm-svn: 146277

rdar://10530851

llvm-svn: 146276

previous commit. It is strange that we see it in 32 bits. We already
have a fixme about it.

llvm-svn: 146273

llvm-svn: 146270

llvm-svn: 146267

llvm-svn: 146266