logic as a QOI cleanup.
rdar://13445327

llvm-svn: 177413

llvm-svn: 177411

llvm-svn: 177410

llvm-svn: 177409

(and possibly others). The attached patch removes it, and tries to
update comments accordingly.

llvm-svn: 177406

Remove an accidentally-added instruction definition and add a comment in the
test case. This is in response to a post-commit review by Bill Schmidt.

No functionality change intended.

llvm-svn: 177404

Lit does support redirects in the 2>&1 style.

llvm-svn: 177403

llvm-svn: 177390

The testing to ensure a vector of zeros of type floating point isn't misclassified as negative zero can be simplified, as pointed out by Duncan Sands.

llvm-svn: 177386

llvm-svn: 177385

The ARM backend currently has poor codegen for long sext/zext
operations, such as v8i8 -> v8i32. This patch addresses this
by performing a custom expansion in ARMISelLowering. It also
adds/changes the cost of such lowering in ARMTTI.

This partially addresses PR14867.

Patch by Pete Couperus

llvm-svn: 177380

llvm-svn: 177379

This reverts commit 82cd8f7382322bee7a71cdc31f7a923c44d37d32.

Just add a comment instead!

llvm-svn: 177377

Make the code more obvious to scan-build and humans.

llvm-svn: 177375

No test case, but should fix a scan_build warning.

llvm-svn: 177374

that we'll prefer to emit the mangled C++ name (pending a clang change).

llvm-svn: 177371

Don't sign extend the immediate value from the OR instruction in
an LIS/OR pair.

llvm-svn: 177361

Also remove unneeded #include and forward declaration.

llvm-svn: 177357

llvm-svn: 177356

llvm-svn: 177351

llvm-svn: 177350

llvm-svn: 177348

parsed one.  Test case coming shortly.
rdar://13446980

llvm-svn: 177347

llvm-svn: 177342

For each compile unit, we want to register a function that will flush that
compile unit. Otherwise, __gcov_flush() would only flush the counters within the
current compile unit, and not any outside of it.

PR15191 & <rdar://problem/13167507>

llvm-svn: 177340

llvm-svn: 177339

PPC64 supports unaligned loads and stores of 64-bit values, but
in order to use the r+i forms, the offset must be a multiple of 4.
Unfortunately, this cannot always be determined by examining the
immediate itself because it might be available only via a TOC entry.

In order to get around this issue, we additionally predicate the
selection of the r+i form on the alignment of the load or store
(forcing it to be at least 4 in order to select the r+i form).

llvm-svn: 177338

The default logic marks them as too expensive.

For example, before this patch we estimated:
  cost of 16 for instruction:   %r = uitofp <4 x i16> %v0 to <4 x float>

While this translates to:
  vmovl.u16 q8, d16
  vcvt.f32.u32  q8, q8

All other costs are left to the values assigned by the fallback logic. Theses
costs are mostly reasonable in the sense that they get progressively more
expensive as the instruction sequences emitted get longer.

radar://13445992

llvm-svn: 177334

Fix cost of some "cheap" cast instructions. Before this patch we used to
estimate for example:
  cost of 16 for instruction:   %r = fptoui <4 x float> %v0 to <4 x i16>

While we would emit:
  vcvt.s32.f32  q8, q8
  vmovn.i32 d16, q8
  vuzp.8  d16, d17

All other costs are left to the values assigned by the fallback logic. Theses
costs are mostly reasonable in the sense that they get progressively more
expensive as the instruction sequences emitted get longer.

radar://13434072

llvm-svn: 177333

Also add some checks to not merge globals used within landing pad instructions or marked as "used".

llvm-svn: 177331

Hal Finkel recently added code to allow unaligned memory references
for PowerPC.  Two tests were temporarily modified with
-disable-ppc-unaligned to keep them from failing.  This patch adjusts
the expected code generation for the unaligned references.

llvm-svn: 177328

llvm-svn: 177327

We hitch a ride with the existing OpndItins class that was used to add
instruction itinerary classes in the many multiclasses in this file.

Use the link provided by the X86FoldableSchedWrite.Folded to find the
right SchedWrite for folded loads.

llvm-svn: 177326

This new-style scheduling information is going to replace the
instruction iteneraries.

This also serves as a test case for Andy's fix in r177317.

llvm-svn: 177323

This handles the case where we have an inbounds GEP with alloca as the pointer.
This fixes the regression in PR12750 and rdar://13286434.
Note that we can also fix this by handling some GEP cases in isKnownNonNull.

llvm-svn: 177321

Properly handle cases where a group of instructions have different
SchedRW lists with the same itinerary class.
This was supposed to work, but I left in an early break.

llvm-svn: 177317

Apparently my final cleanup to use a relevant suffix for these tests before
committing r176831 caused them to stop running since lit wasn't configured to
run tests with that suffix in those directories (why don't we just have a
global suffix list?). So, add the suffix to the relevant directories & fix the
test that has bitrotted over the last week due to my debug info schema changes.

llvm-svn: 177315

llvm-svn: 177314

llvm-svn: 177298

llvm-svn: 177296