llvm-svn: 137246

llvm-svn: 137245

llvm-svn: 137244

data in-register prior to saving to memory.  When we reorder the data in memory
we prevent the need to save multiple scalars to memory, making a single regular
store.

llvm-svn: 137238

llvm-svn: 137237

llvm-svn: 137236

Also, my apologies for spoiling the autocomplete on SimplifyInstructions.cpp. I couldn't think of a better filename.

llvm-svn: 137229

def : Pat<(X86Movss VR128:$src1,
                   (bc_v4i32 (v2i64 (load addr:$src2)))),
          (MOVLPSrm VR128:$src1, addr:$src2)>;
This matches a MOVSS dag with a MOVLPS instruction. However, MOVSS will replace only the low 32 bits of the register, while the MOVLPS instruction will replace the low 64 bits. A testcase is added and illustrates the bug and also modified the one that was already present. Patch by Tanya Lattner.

llvm-svn: 137227

llvm-svn: 137226

llvm-svn: 137225

llvm-svn: 137224

Rewrite some ARM InstrInfo functions to be most accepting of arbitrary register subclasses.  Hopefully this fixes some buildbots.

llvm-svn: 137223

llvm-svn: 137217

llvm-svn: 137204

llvm-svn: 137203

SimplifyIndVar utility since it is required.

llvm-svn: 137202

llvm-svn: 137199

llvm-svn: 137198

based on ScalarEvolution without changing the induction variable phis.

This utility is the main tool of IndVarSimplifyPass, but the pass also
restructures induction variables in strange ways that are sensitive to
pass ordering. This provides a way for other loop passes to simplify
new uses of induction variables created during transformation. The
utility may be used by any pass that preserves ScalarEvolution. Soon
LoopUnroll will use it.

The net effect in this checkin is to cleanup the IndVarSimplify pass
by factoring out the SimplifyIndVar algorithm into a standalone utility.

llvm-svn: 137197

llvm-svn: 137195

llvm-svn: 137194

These are not individual bug fixes. I had to rewrite a good chunk of
the unroller to make it sane. I think it was getting lucky on trivial
completely unrolled loops with no early exits. I included some fairly
simple unit tests for partial unrolling. I didn't do much stress
testing, so it may not be perfect, but should be usable now.

llvm-svn: 137190

llvm-svn: 137189

llvm-svn: 137184

On Cortex-A8, we use the NEON v2f32 instructions for f32 arithmetic. For
better latency, we also send D-register copies down the NEON pipeline by
translating them to vorr instructions.

This patch promotes even S-register copies to D-register copies when
possible so they can also go down the NEON pipeline.  Example:

        vldr.32 s0, LCPI0_0
    loop:
        vorr    d1, d0, d0
    loop2:
        ...
        vadd.f32        d1, d1, d16

The vorr instruction looked like this after regalloc:

    %S2<def> = COPY %S0, %D1<imp-def>

Copies involving odd S-registers, and copies that don't define the full
D-register are left alone.

llvm-svn: 137182

llvm-svn: 137180

llvm-svn: 137179

llvm-svn: 137176

VMCore/BasicBlock.cpp: Don't assume BasicBlock::iterator might end with a non-PHInode Instruction in successors.

Frontends(eg. clang) might pass incomplete form of IR, to step off the way beyond iterator end. In the case I had met, it took infinite loop due to meeting bogus PHInode.

Thanks to Jay Foad and John McCall.

llvm-svn: 137175

llvm-svn: 137174

llvm-svn: 137172

llvm-svn: 137170

Create a new register class for the set of all GPRs except the PC.  Use it to tighten our decoding of BFI.

llvm-svn: 137168

llvm-svn: 137166

llvm-svn: 137163

is the best we can do for these patterns. This fix PR10554.

llvm-svn: 137161

llvm-svn: 137160

functionality since in the C api a pass is created and added to a pass
manager in a single call.

llvm-svn: 137159

Assigned symbol addresses get truncated to 32-bits, even on 64-bit platforms.
That's obviously bogus.
For example,

 .globl _foo
 .equ _foo, 0x987654321ULL


rdar://9922863

llvm-svn: 137158

Not sure about BLXi, but this is what the old disassembler did.

llvm-svn: 137156