llvm-svn: 153160

llvm-svn: 153159

llvm-svn: 153158

i128). In that case, we may not be able to print out the MCExpr as an
expression. For instance, we could have an MCExpr like this:

    0xBEEF0000BEEF0000 | (0xBEEF0000BEEF0000 << 64)

The MCExpr printer handles sizes up to 64-bits, but this expression would
require 128-bits. In this situation, try to evaluate the constant expression and
emit that as the value into 64-bit chunks.
<rdar://problem/11070338>

llvm-svn: 153081

When combining (vextract shuffle (load ), <1,u,u,u>), 0) -> (load ), add users of the final load to the worklist too. Needed by changes I'm preparing to make to X86 backend.

llvm-svn: 153078

a variable. The previous code would break the debug info changing
code invariant. This will regress debug info for arguments where
we elide the alloca created.

Fixes rdar://11066468

llvm-svn: 153074

llvm-svn: 153073

llvm-svn: 153072

llvm-svn: 153071

llvm-svn: 153064

instructions have been scheduled. Handy for tracking down scheduler bugs, or
bugs exposed by scheduling.

llvm-svn: 153045

llvm-svn: 153035

llvm-svn: 152999

This is particularly helpful as both arguments tend to be constants.

llvm-svn: 152991

ScheduleDAGInstrs: When adding uses we add them into a set that's empty at the beginning, no need to maintain another set for the added regs.

llvm-svn: 152934

Saves one machine word on MachineInstr (88->80 bytes on x86_64, 48->44 on i386).

llvm-svn: 152930

No functionality change.

llvm-svn: 152927

These edges are not really necessary, but it is consistent with the
way we currently create physreg edges. Scheduler heuristics that
expect a DAG edge to the block terminator could benefit from this
change. Although in the future I hope we have a better mechanism for
modeling latency across scheduling regions.

llvm-svn: 152895

on our internal nightly testers.  So, basically revert r152486 again.

Abbreviated original commit message:
Implement a more intelligent way of spilling uses across an invoke boundary.

It looks as if Chander's inlining work, r152737, exposed an issue.

llvm-svn: 152887

Revert r152613 (and r152614), "Inline the d'tor and add an anchor instead." for workaround of g++-4.4's miscompilation.

It caused MSP430DAGToDAGISel::SelectIndexedBinOp() to be miscompiled.
When two ReplaceUses()'s are expanded as inline, vtable in base class is stored to latter (ISelUpdater)ISU.

llvm-svn: 152877

the DECL information.

rdar://10855921

llvm-svn: 152876

Part of rdar://8905263

llvm-svn: 152845

llvm-svn: 152844

llvm-svn: 152843

llvm-svn: 152842

llvm-svn: 152841

When optimizing certain BUILD_VECTOR nodes into other BUILD_VECTOR nodes, add the new node into the work list because there is a potential for further optimizations.

llvm-svn: 152784

out the DW_AT_name. Older gdbs unfortunately still use it to
disambiguate member functions in templated classes (gdb.cp/templates.exp).

rdar://11043421 (which is now deferred for a bit)

llvm-svn: 152782

Transform:

        (fsub x, (fadd x, y)) -> (fneg y) and
        (fsub x, (fadd y, x)) -> (fneg y)

if 'unsafe math' is specified.
<rdar://problem/7540295>

llvm-svn: 152777

llvm-svn: 152711

There were cases where a value could be used and it's both crossing an invoke
and NOT crossing an invoke. This could happen in the landing pads. In that case,
we will demote the value to the stack like we did before.
<rdar://problem/10609139>

llvm-svn: 152705

expensive "getFirstTerminator" call. This reduces the time of compilation in
PR12258 from >10 minutes to < 10 seconds.

llvm-svn: 152704

New flags: -misched-topdown, -misched-bottomup. They can be used with
the default scheduler or with -misched=shuffle. Without either
topdown/bottomup flag -misched=shuffle now alternates scheduling
direction.

LiveIntervals update is unimplemented with bottom-up scheduling, so
only -misched-topdown currently works.

Capped the ScheduleDAG hierarchy with a concrete ScheduleDAGMI class.
ScheduleDAGMI is aware of the top and bottom of the unscheduled zone
within the current region. Scheduling policy can be plugged into
the ScheduleDAGMI driver by implementing MachineSchedStrategy.
ConvergingScheduler is now the default scheduling algorithm.
It exercises the new driver but still does no reordering.

llvm-svn: 152700

llvm-svn: 152699

output (we're emitting a specification already and the information
isn't changing).

Saves 1% on the debug information for a build of llvm.

Fixes rdar://11043421

llvm-svn: 152697

Fortify r152675 a bit. Although I'm not able to come up with a test case that would trigger the truncation case.

llvm-svn: 152678

(i16 load $addr+c*sizeof(i16)) and replace uses of (i32 vextract) with the
i16 load. It should issue an extload instead: (i32 extload $addr+c*sizeof(i16)).

rdar://11035895

llvm-svn: 152675

No functionality change.

llvm-svn: 152658

llvm-svn: 152614

llvm-svn: 152613