llvm-svn: 91684

sizes, offsets, and alignments in character units.

llvm-svn: 91683

Patch contributed by Ken Werner of IBM!

llvm-svn: 91681

Patch contributed by Ken Werner of IBM!

llvm-svn: 91680

This works now: (set_option "list_opt", ["val_1", "val_2", "val_3"])

llvm-svn: 91679

llvm-svn: 91678

nested-name specifier name.

I accidentally checked in the test case for this in the last commit ---
fortunately, that refactor was inspired by having debugged this problem already,
so I can fix the bug quick (though probably not fast enough for the buildbots).

llvm-svn: 91677

different functions and pick the function at lookup initialization time.
In theory we could actually divide the criteria functions into N different
functions for the N cases, but it's so not worth it.

Among other things, lets us invoke LookupQualifiedName without recomputing
IDNS info every time.

Do some refactoring in SemaDecl to avoid an awkward special case in LQN
that was only necessary for redeclaration testing for anonymous structs/unions ---
which could be done more efficiently with a scoped lookup anyway.

llvm-svn: 91676

multiple uses.  (The construct in question was found in gcc.)

llvm-svn: 91675

be non-optimal. To be precise, we should avoid folding loads if the instructions
only update part of the destination register, and the non-updated part is not
needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these instructions breaks
the partial register dependency and it can improve performance. e.g.

movss (%rdi), %xmm0
cvtss2sd %xmm0, %xmm0

instead of
cvtss2sd (%rdi), %xmm0

An alternative method to break dependency is to clear the register first. e.g.
xorps %xmm0, %xmm0
cvtss2sd (%rdi), %xmm0

llvm-svn: 91672

clang -cc1: Rename -mcpu to -target-cpu to match other target options and not alias driver/backend option.

llvm-svn: 91671

llvm-svn: 91670

new InitializationSequence. This fixes some bugs (e.g., PR5808),
changed some diagnostics, and caused more churn than expected. What's
new:

  - InitializationSequence now has a "C conversion sequence" category
    and step kind, which falls back to
  - Changed the diagnostics for returns to always have the result type
    of the function first and the type of the expression second.
    CheckSingleAssignmentConstraints to peform checking in C. 
  - Improved ASTs for initialization of return values. The ASTs now
    capture all of the temporaries we need to create, but
    intentionally do not bind the tempoary that is actually returned,
    so that it won't get destroyed twice.
  - Make sure to perform an (elidable!) copy of the class object that
    is returned from a class.
  - Fix copy elision in CodeGen to properly see through the
    subexpressions that occur with elidable copies.
  - Give "new" its own entity kind; as with return values and thrown
    objects, we don't bind the expression so we don't call a
    destructor for it.

Note that, with this patch, I've broken returning move-only types in
C++0x. We'll fix it later, when we tackle NRVO.

llvm-svn: 91669

is not reassociative.

llvm-svn: 91667

llvm-svn: 91666

llvm-svn: 91664

Integer negation only overflows with INT_MIN, but that's an important case.

llvm-svn: 91662

to compile a translation unit into the debug info for that file.
 - Used by parts of Darwin build process to check compiler flags, etc.
 - <rdar://problem/7256886> clang does not emit AT_APPLE_flags

llvm-svn: 91661

llvm-svn: 91659

llvm-svn: 91658

llvm-svn: 91657

llvm-svn: 91656

llvm-svn: 91655

contains another loop, or an instruction. The loop form is
substantially more efficient on large loops than the typical
code it replaces.

llvm-svn: 91654

llvm-svn: 91653

(radar 7482224).
 

llvm-svn: 91652

llvm-svn: 91651

with unreachable.

llvm-svn: 91650

The change in SelectionDAGBuilder is needed to allow using bitcasts to convert
between f64 (the default type for ARM "d" registers) and 64-bit Neon vector
types.  Radar 7457110.

llvm-svn: 91649

This protects this test from depending on codegen not performing the
tail call optimization by default.

llvm-svn: 91648

llvm-svn: 91647

llvm-svn: 91645

(0 && "error").  Rough consensus seems to be that g++ *should* be diagnosing
this because the pointer makes it not an ICE in c++03.  Everyone agrees that
the current standard is silly and null-pointer-ness should not be based on
ICE-ness.  Excellent fight scene in Act II, denouement weak, two stars.

llvm-svn: 91644

llvm-svn: 91643

llvm-svn: 91642

of 91296 that caused trouble -- the Processed list needs to be
preserved for the livetime of the pass, as AddUsersIfInteresting
is called from other passes.

llvm-svn: 91641

(http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20091214/092780.html)
The instruction fixes were checked and approved by Chris Lattner, but
these testcase fixes are mine; please yell at me if there are any
problems with either.

* PR5050-constructor-conversion.cpp
* array-construction.cpp
* constructor-conversion.cpp
* cast-conversion.cpp
* constructor-default-arg.cpp
* derived-to-base-conv.cpp
* ptr-to-member-function.cpp
* call-arg-zero-temp.cpp
* default-destructor-synthesis.cpp
* global-array-destruction.cpp
* array-operator-delete-call.cpp
* decl-ref-init.cpp
* default-constructor-for-members.cpp
* convert-to-fptr.cpp
* constructor-for-array-members.cpp
* conversion-function.cpp
* objc-read-weak-byref.m
	Fixed testcase to reflect call qualifier

llvm-svn: 91640

llvm-svn: 91639

X86 instruction tables.

Also (while I was at it) cleaned up the X86 tables, removing tabs and
80-line violations.

This patch was reviewed by Chris Lattner, but please let me know if
there are any problems.

* X86*.td
	Removed tabs and fixed 80-line violations

* X86Instr64bit.td
	(IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW)
		Added
	(CALL, CMOV) Added qualifiers
	(JMP) Added PC-relative jump instruction
	(POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate
		that it is 64-bit only (ambiguous since it has no
		REX prefix)
	(MOV) Added rr form going the other way, which is encoded
		differently
	(MOV) Changed immediates to offsets, which is more correct;
		also fixed MOV64o64a to have to a 64-bit offset
	(MOV) Fixed qualifiers
	(MOV) Added debug-register and condition-register moves
	(MOVZX) Added more forms
	(ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which
		(as with MOV) are encoded differently
	(ROL) Made REX.W required
	(BT) Uncommented mr form for disassembly only
	(CVT__2__) Added several missing non-intrinsic forms
	(LXADD, XCHG) Reordered operands to make more sense for
		MRMSrcMem
	(XCHG) Added register-to-register forms
	(XADD, CMPXCHG, XCHG) Added non-locked forms
* X86InstrSSE.td
	(CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ)
		Added
* X86InstrFPStack.td
	(COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP,
	 FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X,
	 FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM,
	 FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE,
	 FXRSTOR)
		Added
	(FCOM, FCOMP) Added qualifiers
	(FSTENV, FSAVE, FSTSW) Fixed opcode names
	(FNSTSW) Added implicit register operand
* X86InstrInfo.td
	(opaque512mem) Added for FXSAVE/FXRSTOR
	(offset8, offset16, offset32, offset64) Added for MOV
	(NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR,
	 LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS,
	 LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT,
	 LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC,
	 CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC,
	 SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL,
	 VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD,
	 VMWRITE, VMXOFF, VMXON) Added
	(NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier
	(JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL,
	 JGE, JLE, JG, JCXZ) Added 32-bit forms
	(MOV) Changed some immediate forms to offset forms
	(MOV) Added reversed reg-reg forms, which are encoded
		differently
	(MOV) Added debug-register and condition-register moves
	(CMOV) Added qualifiers
	(AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV
	(BT) Uncommented memory-register forms for disassembler
	(MOVSX, MOVZX) Added forms
	(XCHG, LXADD) Made operand order make sense for MRMSrcMem
	(XCHG) Added register-register forms
	(XADD, CMPXCHG) Added unlocked forms
* X86InstrMMX.td
	(MMX_MOVD, MMV_MOVQ) Added forms
* X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table
	change

* X86RegisterInfo.td: Added debug and condition register sets
* x86-64-pic-3.ll: Fixed testcase to reflect call qualifier
* peep-test-3.ll: Fixed testcase to reflect test qualifier
* cmov.ll: Fixed testcase to reflect cmov qualifier
* loop-blocks.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-11.ll: Fixed testcase to reflect call qualifier
* 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call
  qualifier
* x86-64-pic-2.ll: Fixed testcase to reflect call qualifier
* live-out-reg-info.ll: Fixed testcase to reflect test qualifier
* tail-opts.ll: Fixed testcase to reflect call qualifiers
* x86-64-pic-10.ll: Fixed testcase to reflect call qualifier
* bss-pagealigned.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-1.ll: Fixed testcase to reflect call qualifier
* widen_load-1.ll: Fixed testcase to reflect call qualifier

llvm-svn: 91638

llvm-svn: 91636