- May 20, 2010
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Daniel Dunbar authored
it. llvm-svn: 104270
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- May 06, 2010
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Sean Callanan authored
and %rcr_, leaving just %cr_ which is what people expect. Updated the disassembler to support this unified register set. Added a testcase to verify that the registers continue to be decoded correctly. llvm-svn: 103196
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- Apr 07, 2010
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Sean Callanan authored
argument that had to be between 0 and 7 to have any value, firing an assert later in the AsmPrinter. Now, the disassembler rejects instructions with out-of-range values for that immediate. llvm-svn: 100694
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- Mar 14, 2010
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Evan Cheng authored
llvm-svn: 98468
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- Feb 24, 2010
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Sean Callanan authored
disassembler never recognizes InitReg instructions. llvm-svn: 97017
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- Feb 13, 2010
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Sean Callanan authored
tables. llvm-svn: 96073
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Sean Callanan authored
llvm-svn: 96065
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Chris Lattner authored
fix swapgs to be spelled right. llvm-svn: 96058
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Chris Lattner authored
encoder and decoder by using new MRM_ forms. llvm-svn: 96048
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Sean Callanan authored
whose opcodes extend into the ModR/M field using the Form field of the instruction rather than by special casing each instruction. Commented out the special casing of VMCALL, which is the first instruction to use this special form. While I was in the neighborhood, added a few comments for people modifying the Intel disassembler. llvm-svn: 96043
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- Feb 12, 2010
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Chris Lattner authored
This will work better for the disassembler for modeling things like lfence/monitor/vmcall etc. llvm-svn: 95960
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- Feb 10, 2010
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Chris Lattner authored
for representing constraint info semantically instead of as a c expression that will be blatted out to the .inc file. Fix X86RecognizableInstr to use this instead of parsing C code :). llvm-svn: 95753
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- Dec 22, 2009
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Sean Callanan authored
Made LEA memory operands emit only 4 MCInst operands. Made the scale operand equal 1 for instructions that have no SIB byte. llvm-svn: 91919
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- Dec 19, 2009
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Daniel Dunbar authored
llvm-svn: 91756
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Sean Callanan authored
incarnations), integrated into the MC framework. The disassembler is table-driven, using a custom TableGen backend to generate hierarchical tables optimized for fast decode. The disassembler consumes MemoryObjects and produces arrays of MCInsts, adhering to the abstract base class MCDisassembler (llvm/MC/MCDisassembler.h). The disassembler is documented in detail in - lib/Target/X86/Disassembler/X86Disassembler.cpp (disassembler runtime) - utils/TableGen/DisassemblerEmitter.cpp (table emitter) You can test the disassembler by running llvm-mc -disassemble for i386 or x86_64 targets. Please let me know if you encounter any problems with it. llvm-svn: 91749
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