could only get undefs and the vector shuffle becomes an undef,
generating wrong code.

llvm-svn: 137295

Fix X86TargetLowering::LowerExternalSymbol so that it actually works in non-trivial cases.  This hasn't been an issue before because the function isn't normally called (but apparently is used to generate a tail-call to sin() on ELF x86-32 with PIC and SSE2).

Fixes PR9693.

llvm-svn: 137292

data in-register prior to saving to memory.  When we reorder the data in memory
we prevent the need to save multiple scalars to memory, making a single regular
store.

llvm-svn: 137238

llvm-svn: 137194

llvm-svn: 137179

is the best we can do for these patterns. This fix PR10554.

llvm-svn: 137161

llvm-svn: 137127

llvm-svn: 137114

llvm-svn: 137090

llvm-svn: 137067

llvm-svn: 136899

Fixes PR10527.

llvm-svn: 136853

llvm-svn: 136803

The testcase looks extremely fragile, so I'm adding an assertion which should catch any cases like this.

llvm-svn: 136711

  shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
To:
  shuffle (vload ptr)), undef, <1, 1, 1, 1>
Fix PR10494

llvm-svn: 136691

the legalizer. This commit together with the two previous ones fixes
PR10495.

llvm-svn: 136654

llvm-svn: 136653

using a stack store.

llvm-svn: 136652

avoid returning early for v8i32 types, which would only be valid for
vector with all zeros. Also split the handling of zeros and ones into separate
checking logic since they are handled differently. This fixes PR10547

llvm-svn: 136642

working on x86 (at least for trivial testcases); other architectures will
need more work so that they actually emit the appropriate instructions for
orderings stricter than 'monotonic'. (As far as I can tell, the ARM, PPC,
Mips, and Alpha backends need such changes.)

llvm-svn: 136457

on the second half must be reindexed.

llvm-svn: 136454

generation to always catch the weird cases.

llvm-svn: 136453

llvm-svn: 136452

undef mask elements. This fixes PR10529.

llvm-svn: 136450

Also tidy up code a bit.

llvm-svn: 136449

Also make PALIGNR masks to don't match 256-bits, which isn't supported
It's also a step to solve PR10489

llvm-svn: 136448

llvm-svn: 136324

a convert pattern close to the instruction definition.

llvm-svn: 136320

llvm-svn: 136283

C++0x.

llvm-svn: 136211

llvm-svn: 136201

usage of the shuffle bitmask. Both work in 128-bit lanes without
crossing, but in the former the mask of the high part is the same
used by the low part while in the later both lanes have independent
masks. Handle this properly and and add support for vpermilpd.

llvm-svn: 136200

On x86 we can't encode an immediate LHS of a sub directly. If the RHS comes from a XOR with a constant we can
fold the negation into the xor and add one to the immediate of the sub. Then we can turn the sub into an add,
which can be commuted and encoded efficiently.

This code is generated for __builtin_clz and friends.

llvm-svn: 136167

different from the previous 128-bit because they work in lanes.
Update a few comments and add testcases

llvm-svn: 136157

Prevent x86-specific DAGCombine from creating nodes with illegal type (which could not be selected).  Fixes a minor isel issue that was breaking the testcase from r136130.

llvm-svn: 136148

support for 256-bit versions (but no instruction selection yet, coming next).

llvm-svn: 136050

llvm-svn: 136049

This also fixes PR10452

llvm-svn: 136004

shuffle before inserting on a 256-bit vector.
- Add AVX versions of movd/movq instructions
- Introduce a few COPY patterns to match insert_subvector instructions.
This turns a trivial insert_subvector instruction into a register copy,
coalescing the xmm into a ymm and avoid emiting on more instruction.

llvm-svn: 136002

native 256-bit vector instruction to do scalar_to_vector.

llvm-svn: 136001