llvm-svn: 47545

not safe.  This is fixed by more aggressively checking that the return slot is
not used elsewhere in the function.

llvm-svn: 47544

llvm-svn: 47542

Fix an issue where GVN would try to use an instruction before its definition when performing return slot optimization.

llvm-svn: 47541

out of illegal elements (BUILD_VECTOR).  Uses and beefs
up BUILD_PAIR, though it didn't really have to.  Like
most of LegalizeTypes, does not support soft-float.
This cures all "make check" vector building failures.

llvm-svn: 47537

%r3 on PPC) in their ASM files. However, it's hard for humans to read
during debugging. Adding a new field to the register data that lets you
specify a different name to be printed than the one that goes into the
ASM file -- %x3 instead of %r3, for instance.

llvm-svn: 47534

llvm-svn: 47533

for CellSPU modifications:

- SPUInstrInfo.td refactoring: "multiclass" really is _your_ friend.
- Other improvements based on refactoring effort in SPUISelLowering.cpp,
  esp. in SPUISelLowering::PerformDAGCombine(), where zero amount shifts and
  rotates are now eliminiated, other scalar-to-vector-to-scalar silliness
  is also eliminated.
- 64-bit operations are being implemented, _muldi3.c gcc runtime now
  compiles and generates the right code. More work still needs to be done.

llvm-svn: 47532

llvm-svn: 47529

If remating a machine instr with virtual register operand, make sure the vr is avaliable at all uses regardless of whether it would be folded.

llvm-svn: 47526

llvm-svn: 47524

invalid command-line options.

llvm-svn: 47523

No need recognize load from a fixed argument slot as re-materializable. LiveIntervalAnalysis already handles it as a special case.

llvm-svn: 47522

llvm-svn: 47521

Recognize loads of arguments as re-materializable first. Therefore if isReallyTriviallyReMaterializable() returns true it doesn't confuse it as a "normal" re-materializable instruction.

llvm-svn: 47520

llvm-svn: 47519

llvm-svn: 47518

llvm-svn: 47517

llvm-svn: 47514

llvm-svn: 47511

llvm-svn: 47509

To support multiple return values, now ret instruction supports multiple operands instead of one aggregate operand.

llvm-svn: 47508

llvm-svn: 47507

stuff into ParamAttrsList.h.  Per feedback from
ParamAttrs changes.

llvm-svn: 47504

llvm-svn: 47500

Really really bad local register allocator bug. On X86, it was never using ESI, EDI, and EBP because of a bug in RALocal::isPhysRegAvailable(). For example, when
it checks if ESI is available, it then looks at registers aliases to ESI. SIL is marked -2 (not allocatable) but isPhysRegAvailable() incorrectly assumes it is in use and returns false for ESI.

llvm-svn: 47499

llvm-svn: 47496

llvm-svn: 47495

llvm-svn: 47494

llvm-svn: 47492

llvm-svn: 47485

the way through.  It is now used for codegen.

llvm-svn: 47484

llvm-svn: 47483

llvm-svn: 47479

llvm-svn: 47478

llvm-svn: 47476

the definition of the operand also reaches its uses.

llvm-svn: 47475

instead of with mmx registers.  This horribleness is apparently
done by gcc to avoid having to insert emms in places that really 
should have it.  This is the second half of rdar://5741668.

llvm-svn: 47474

llvm-svn: 47473

llvm-svn: 47472