yet, only assembly encoding support.

llvm-svn: 105521

llvm-svn: 105519

llvm-svn: 105496

llvm-svn: 105488

llvm-svn: 105461

llvm-svn: 105456

Add skeleton of support for emitting the list of prototypes for BuiltinsARM.def

llvm-svn: 105443

llvm-svn: 105416

A temporary flag -arm-tail-calls defaults to off,
so there is no functional change by default.
Intrepid users may try this; simple cases work
but there are bugs.

llvm-svn: 105413

llvm-svn: 105396

llvm-svn: 105390

implementation. Force the internal one to unbreak clang selfhost on linux.

llvm-svn: 105386

arm_neon.h now makes it through clang and generates appropriate code for those functions which can use
generic vector operators rather than __builtin_neon_*

llvm-svn: 105380

llvm-svn: 105355

llvm-svn: 105354

llvm-svn: 105353

OSX users: make sure that CrashReporter is disabled when running unit tests.
Death tests are enabled now so you'll get a ton of message boxes.

llvm-svn: 105352

llvm-svn: 105349

llvm-svn: 105318

llvm-svn: 105316

llvm-svn: 105315

llvm-svn: 105307

llvm-svn: 105297

llvm-svn: 105270

llvm-svn: 105225

EOF is detected.

llvm-svn: 105223

The StmtNodes generator has been generalized to allow for the
creation of DeclNodes tables as well, and another emitter was
added for DeclContexts.

llvm-svn: 105164

Also verify that all subregister indices compose unambiguously.

llvm-svn: 105064

llvm-svn: 104927

llvm-svn: 104912

of the intrinsics.  The goal is to auto-generate both support for GCC-style (vector)
and ARM-style (struct of vector) intrinsics.

This is work in progress, but will be completed soon.

llvm-svn: 104910

raw_ostream doesn't try to do its own error handling.

llvm-svn: 104881

llvm-svn: 104874

llvm-svn: 104845

llvm-svn: 104806

llvm-svn: 104755

This means that our Registers are now ordered R7, R8, R9, R10, R12, ...
Not R1, R10, R11, R12, R2, R3, ...

llvm-svn: 104745

llvm-svn: 104741

A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.

CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.

It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.

llvm-svn: 104704

This reverts commit 104654.

llvm-svn: 104660