Revert part of r141274. Only need to change encoding for xchg %eax, %eax in 64-bit mode. This is because in 64-bit mode xchg %eax, %eax implies zeroing the upper 32-bits of RAX which makes it not a NOP. In 32-bit mode using NOP encoding is fine.

llvm-svn: 141353

llvm-svn: 141342

others. They take the call site value. Determine if it's a proper value. And
then jumps to the correct call site via a jump table.

llvm-svn: 141341

Fix the check for nested IT instructions in the disassembler.  We need to perform the check before adding the Thumb predicate, which pops on entry off the ITBlock queue.

llvm-svn: 141339

llvm-svn: 141333

llvm-svn: 141327

llvm-svn: 141323

llvm-svn: 141321

Place the immediate to OR into a register so that it works.

llvm-svn: 141319

llvm-svn: 141318

* Some code cleanup.

llvm-svn: 141317

llvm-svn: 141316

Fix VarListElementInit::resolveListElementReference to return a
partially resolved VarListElementInint in the case where full
resolution is not possible.  This allows TableGen to make forward
progress resolving certain complex list expressions.

llvm-svn: 141315

Check that all ADD patters are processed.

Add a SUB test.

llvm-svn: 141314

llvm-svn: 141313

llvm-svn: 141306

llvm-svn: 141305

llvm-svn: 141299

Compare the entire keyword string.

llvm-svn: 141295

llvm-svn: 141294

llvm-svn: 141293

They are not in sync now, for example Bitcast would show up as LLVMCall.
So instead introduce 2 functions that map to and from the opcodes in the C
bindings.

llvm-svn: 141290

llvm-svn: 141289

llvm-svn: 141288

llvm-svn: 141287

llvm-svn: 141286

llvm-svn: 141285

llvm-svn: 141284

llvm-svn: 141283

Fix assembling of xchg %eax, %eax to not use the NOP encoding of 0x90. This was done by creating a new register group that excludes AX registers. Fixes PR10345. Also added aliases for flipping the order of the operands of xchg <reg>, %eax.

llvm-svn: 141274

llvm-svn: 141269

llvm-svn: 141266

to an infinite loop because of the def-use chains.

Also use a frame load instead of store for the LD instruction.

llvm-svn: 141263

This restores my karma after I added TRI::getSubClassWithSubReg().

Register constraints are applied 'backwards'.  Starting from the
register class required by an instruction operand, the correct question
is: 'How can I constrain the super-register register class so all its
sub-registers satisfy the instruction constraint?' The
getMatchingSuperRegClass() hook answers that.

We never need to go 'forwards': Starting from a super-register register
class, what register class are the sub-registers in?  The
getSubRegisterRegClass() hook did that.

llvm-svn: 141258

llvm-svn: 141248

merging an lsl #2 that has multiple uses on A9. This shift is free, so there is
no problem merging it in multiple places. Other unprofitable shifts will not be
merged.

llvm-svn: 141247

number (18) for the proper addressing mode.

llvm-svn: 141245

llvm-svn: 141244

Fix the argument passed in the multidef example.

llvm-svn: 141243

For consistency, prefix multiclass template arg names with the
multiclass name followed by "::" to avoid name clashes among
multiclass arguments and other entities in the multiclass.

llvm-svn: 141239