Match expectations of the new latency API. Cleanup and make the logic consistent.

llvm-svn: 158163

llvm-svn: 158162

llvm-svn: 158161

It will cause assertion failure later on.

llvm-svn: 158160

Fixes pr13048.

llvm-svn: 158158

This patch will optimize the following
    movq    %rdi, %rax
    subq    %rsi, %rax
    cmovsq  %rsi, %rdi
    movq    %rdi, %rax
to
    cmpq    %rsi, %rdi
    cmovsq  %rsi, %rdi
    movq    %rdi, %rax

Perform this optimization if the actual result of SUB is not used.

rdar: 11540023
llvm-svn: 158126

The commit is intended to fix rdar://11540023.
It is implemented as part of peephole optimization. We can actually implement
this in the SelectionDAG lowering phase.

llvm-svn: 158122

LLVM is now -Wunused-private-field clean except for
- lib/MC/MCDisassembler/Disassembler.h. Not sure why it keeps all those unaccessible fields.
- gtest.

llvm-svn: 158096

There are some that I didn't remove this round because they looked like
obvious stubs. There are dead variables in gtest too, they should be
fixed upstream.

llvm-svn: 158090

X86.
rdar://11496434

llvm-svn: 158087

llvm-svn: 158055

llvm-svn: 158049

Minimum latency determines per-cycle scheduling groups.
Expected latency determines critical path and cost.

llvm-svn: 158021

llvm-svn: 158013

llvm-svn: 158004

llvm-svn: 157981

llvm-svn: 157980

This allows a subtarget to explicitly specify the issue width and
other properties without providing pipeline stage details for every
instruction.

llvm-svn: 157979

llvm-svn: 157976

llvm-svn: 157972

when a compile time constant is known.  This occurs when implicitly zero 
extending function arguments from 16 bits to 32 bits.

<rdar://problem/11481151>

llvm-svn: 157966

inserted after the shift-left-logical node.

llvm-svn: 157937

llvm-svn: 157935

This was mostly done already in r156162, but I missed one place.

llvm-svn: 157929

llvm-svn: 157920

llvm-svn: 157917

Add VFMADDSUB and VFMSUBADD FMA instructions to folding tables. Also add 213 forms of scalar FMA instructions.

llvm-svn: 157914

llvm-svn: 157912

It seems that this no longer causes test suite failures on PPC64 (after r157159),
and often gives a performance benefit, so it can be enabled by default.

llvm-svn: 157911

llvm-svn: 157903

Rename fma4 intrinsics to just fma since they are now used for both FMA4 and FMA3. Autoupgrade support coming in a separate commit.

llvm-svn: 157898

llvm-svn: 157896

Use sse_load_f32/64 for scalar FMA3 intrinsic patterns instead of 128-bit loads to match instruction behavior.

llvm-svn: 157895

llvm-svn: 157894

llvm-svn: 157885

llvm-svn: 157872

llvm-svn: 157867

llvm-svn: 157866

llvm-svn: 157865

custom-lower unaligned load and store nodes.

llvm-svn: 157864