- Jan 02, 2012
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Craig Topper authored
Miscellaneous shuffle lowering cleanup. No functional changes. Primarily converting the indexing loops to unsigned to be consistent across functions. llvm-svn: 147430
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Craig Topper authored
Make CanXFormVExtractWithShuffleIntoLoad reject loads with multiple uses. Also make it return false if there's not even a load at all. This makes the code better match the code in DAGCombiner that it tries to match. These two changes prevent some cases where vector_shuffles were making it to instruction selection and causing the older shuffle selection code to be triggered. Also needed to fix a bad pattern that this change exposed. This is the first step towards getting rid of the old shuffle selection support. No test cases yet because there's no way to tell whether a shuffle was handled in the legalize stage or at instruction selection. llvm-svn: 147428
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Chandler Carruth authored
build. This didn't show up in the CMake build because the CMake build for the unittests is rather poorly factored. This probably isn't the correct fix. This should be a bitcode reader unittest not a VMCore unittest. I'll move it and clean various parts of the unittest up in a follow-up patch, but I wanted to unbreak the bots. llvm-svn: 147427
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Nadav Rotem authored
Optimize the sequence blend(sign_extend(x)) to blend(shl(x)) since SSE blend instructions only look at the highest bit. llvm-svn: 147426
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Rafael Espindola authored
PR11677. llvm-svn: 147425
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- Jan 01, 2012
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Craig Topper authored
llvm-svn: 147411
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Craig Topper authored
Fix sfence, lfence, mfence, and clflush to be able to be selected when AVX is enabled. Fix monitor and mwait to require SSE3 or AVX, previously they worked even if SSE3 was disabled. Make prefetch instructions not set the execution domain since they don't use XMM registers. llvm-svn: 147409
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Benjamin Kramer authored
llvm-svn: 147404
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Benjamin Kramer authored
PatternMatch: Introduce a matcher for instructions with the "exact" bit. Use it to simplify a few matchers. llvm-svn: 147403
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Benjamin Kramer authored
llvm-svn: 147402
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Rafael Espindola authored
llvm-svn: 147400
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Elena Demikhovsky authored
The failure seen on win32, when i64 type is illegal. It happens on stage of conversion VECTOR_SHUFFLE to BUILD_VECTOR. The failure message is: llc: SelectionDAG.cpp:784: void VerifyNodeCommon(llvm::SDNode*): Assertion `(I->getValueType() == EltVT || (EltVT.isInteger() && I->getValueType().isInteger() && EltVT.bitsLE(I->getValueType()))) && "Wrong operand type!"' failed. I added a special test that checks vector shuffle on win32. llvm-svn: 147399
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NAKAMURA Takumi authored
llvm-svn: 147395
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Craig Topper authored
llvm-svn: 147394
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Craig Topper authored
llvm-svn: 147393
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Craig Topper authored
Fix typo in a SHUFPD and VSHUFPD pattern that prevented SHUFPD/VSHUFPD with a load from being selected. llvm-svn: 147392
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- Dec 31, 2011
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Nick Lewycky authored
'and' that would zero out the trailing bits, and to produce an exact shift ourselves. llvm-svn: 147391
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Dylan Noblesmith authored
See PR11652. Trying to add this assert to setSubclassData() itself actually prevented the miscompile entirely, so it has to be here. This makes the source of the bug more obvious than the other asserts triggering later on did. llvm-svn: 147390
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- Dec 30, 2011
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Bruno Cardoso Lopes authored
llvm-svn: 147383
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Bruno Cardoso Lopes authored
Implement encoder methods getJumpTargetOpValue and getBranchTargetOpValue for jmptarget and brtarget Mips tablegen operand types in the code emitter for old-style JIT. Rename the pc relative relocation for branches - new name is Mips::reloc_mips_pc16. Patch by Sasa Stankovic llvm-svn: 147382
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Nick Lewycky authored
llvm-svn: 147379
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Craig Topper authored
Make FMA4 imply AVX so that YMM registers would be available. Necessitates removing from Bulldozer CPU types since it would enable AVX code generation implicitly. Also make SSE4A imply SSE3. Without some level of SSE implied, XMM registers wouldn't be legal. llvm-svn: 147369
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Craig Topper authored
llvm-svn: 147368
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Craig Topper authored
llvm-svn: 147367
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Craig Topper authored
Separate the concept of having memory access in operand 4 from the concept of having the W bit set for XOP instructons. Removes ORing W-bits in the encoder and will similarly simplify the disassembler implementation. llvm-svn: 147366
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Craig Topper authored
llvm-svn: 147365
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Craig Topper authored
llvm-svn: 147364
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Craig Topper authored
Change FMA4 memory forms to use memopv* instead of alignedloadv*. No need to force alignment on these instructions. Add a couple testcases for memory forms. llvm-svn: 147361
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Craig Topper authored
Fix load size for FMA4 SS/SD instructions. They need to use f32 and f64 size, but with the special handling to be compatible with the intrinsic expecting a vector. Similar handling is already used elsewhere. llvm-svn: 147360
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Hal Finkel authored
1. The ST*UX instructions that store and update the stack pointer did not set define/kill on R1. This became a problem when I activated post-RA scheduling (and had incorrectly adjusted the Frames-large test). 2. eliminateFrameIndex did not kill its scavenged temporary register, and this could cause the scavenger to exhaust all available registers (and its emergency spill slot) when there were a lot of CR values to spill. The 2010-02-12-saveCR test has been adjusted to check for this. llvm-svn: 147359
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- Dec 29, 2011
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Rafael Espindola authored
llvm-svn: 147356
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Rafael Espindola authored
llvm-svn: 147354
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Craig Topper authored
llvm-svn: 147353
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Rafael Espindola authored
llvm-svn: 147352
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Craig Topper authored
llvm-svn: 147351
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Craig Topper authored
Make FMA3 imply AVX needs to be enabled. Particularly because 256-bit types aren't valid unless AVX is enabled. llvm-svn: 147349
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Craig Topper authored
llvm-svn: 147348
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Craig Topper authored
llvm-svn: 147347
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Craig Topper authored
Mark non-VEX forms of PCLMUL instructions as requiring SSE2 to be enabled along with CLMUL. That's required for the XMM registers to be valid for integer data. Doesn't change any behavior since the CLMUL instructions don't have patterns yet. llvm-svn: 147345
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Craig Topper authored
Mark non-VEX forms of AES instructions as requiring SSE2 to be enabled along with AES. Since that's required for the XMM registers to be valid for integer data. Doesn't change any behavior though since you can't use an intrinsic with an illegal type anyway. Just makes it consistent with the VEX forms. llvm-svn: 147344
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