add sldt GR32, which isn't documented in the intel manual
but which gas accepts.  Part of rdar://8418316

llvm-svn: 113938

llvm-svn: 113937

llvm-svn: 113936

version because it adds a prefix and makes even less sense
than the other broken forms.  This wraps up rdar://8431422

llvm-svn: 113932

llvm-svn: 113930

rdar://8431422

llvm-svn: 113929

instead of crashing.  This fixes:
rdar://8431815 - crash when invalid operand is one that isn't present

llvm-svn: 113921

storeRegToStackSlot.

llvm-svn: 113918

llvm-svn: 113915

llvm-svn: 113914

attribute(used).

llvm-svn: 113911

"The register specified for a dregpair is the corresponding Q register, so to
get the pair, we need to look up the sub-regs based on the qreg. Create a
lookup function since we don't have access to TargetRegisterInfo here to
be able to use getSubReg(ARM::dsub_[01])."

Additionaly, fix the NEON VLD1* and VST1* instruction patterns not to use
the dregpair modifier for the 2xdreg versions. Explicitly specifying the two
registers as operands is more correct and more consistent with the other
instruction patterns. This enables further cleanup of special case code in the
disassembler as a nice side-effect.

llvm-svn: 113903

This fixes PR8114

llvm-svn: 113894

llvm-svn: 113892

that needs to be shared a bit more widely around.

llvm-svn: 113886

change.

llvm-svn: 113878

llvm-svn: 113877

llvm-svn: 113876

get the pair, we need to look up the sub-regs based on the qreg. Create a
lookup function since we don't have access to TargetRegisterInfo here to
be able to use getSubReg(ARM::dsub_[01]).

llvm-svn: 113875

llvm-svn: 113867

llvm-svn: 113860

isn't a good level of abstraction for memdep. Instead, generalize
AliasAnalysis::alias and related interfaces with a new Location
class for describing a memory location. For now, this is the same
Pointer and Size as before, plus an additional field for a TBAA tag.

Also, introduce a fixed MD_tbaa metadata tag kind.

llvm-svn: 113858

llvm-svn: 113857

llvm-svn: 113856

an argument, so that we can distinguish instructions with the same register
classes but different numbers of registers (e.g., vld3 and vld4).  Fix some
of the non-pseudo NEON ld/st instruction itineraries to reflect the number
of registers loaded or stored, not just the opcode name.

llvm-svn: 113854

on by default and has received significant testing.

llvm-svn: 113852

llvm-svn: 113849

llvm-svn: 113848

llvm-svn: 113847

llvm-svn: 113846

Use frame index, if available for byval argument while lowering dbg_declare. Otherwise let getRegForValue() find register for this argument.

llvm-svn: 113843

by morphing the 'and' to its recording form 'andS'.

This is basically a test commit into this area, to
see whether the bots like me. Several generalizations
can be applied and various avenues of code simplification
are open. I'll introduce those as I go.

I am aware of stylistic input from Bill Wendling, about
where put the analysis complexity, but I am positive
that we can move things around easily and will find a
satisfactory solution.

llvm-svn: 113839

llvm-svn: 113837

This may produce warnings on MSVS, but it's better than failures.

llvm-svn: 113834

llvm-svn: 113833

non-function-local value, it may result in the metadata no longer needing to be
function-local. Check for this condition, and clear the isFunctionLocal flag, if
it's still in the uniquing map, since any node in the uniquing map needs to have
an accurate function-local flag.

Also, add an assert to help catch problematic cases.

llvm-svn: 113828

deleted.  Fix this by doing the copyValue's before we delete stuff!

The testcase only repros the problem on my system with valgrind.

llvm-svn: 113820

This reverts commit r113632

Conflicts:

	cmake/modules/AddLLVM.cmake

llvm-svn: 113819

register allocation.  Remove the NEONPreAllocPass, which is no longer needed.
Yeah!!

llvm-svn: 113818

edited without actually using LiveIntervalMap functionality.

llvm-svn: 113816