add sldt GR32, which isn't documented in the intel manual
but which gas accepts.  Part of rdar://8418316

llvm-svn: 113938

llvm-svn: 113937

llvm-svn: 113936

version because it adds a prefix and makes even less sense
than the other broken forms.  This wraps up rdar://8431422

llvm-svn: 113932

llvm-svn: 113930

rdar://8431422

llvm-svn: 113929

instead of crashing.  This fixes:
rdar://8431815 - crash when invalid operand is one that isn't present

llvm-svn: 113921

storeRegToStackSlot.

llvm-svn: 113918

llvm-svn: 113915

llvm-svn: 113914

"The register specified for a dregpair is the corresponding Q register, so to
get the pair, we need to look up the sub-regs based on the qreg. Create a
lookup function since we don't have access to TargetRegisterInfo here to
be able to use getSubReg(ARM::dsub_[01])."

Additionaly, fix the NEON VLD1* and VST1* instruction patterns not to use
the dregpair modifier for the 2xdreg versions. Explicitly specifying the two
registers as operands is more correct and more consistent with the other
instruction patterns. This enables further cleanup of special case code in the
disassembler as a nice side-effect.

llvm-svn: 113903

This fixes PR8114

llvm-svn: 113894

that needs to be shared a bit more widely around.

llvm-svn: 113886

change.

llvm-svn: 113878

llvm-svn: 113877

llvm-svn: 113876

get the pair, we need to look up the sub-regs based on the qreg. Create a
lookup function since we don't have access to TargetRegisterInfo here to
be able to use getSubReg(ARM::dsub_[01]).

llvm-svn: 113875

llvm-svn: 113867

llvm-svn: 113860

llvm-svn: 113857

llvm-svn: 113856

an argument, so that we can distinguish instructions with the same register
classes but different numbers of registers (e.g., vld3 and vld4).  Fix some
of the non-pseudo NEON ld/st instruction itineraries to reflect the number
of registers loaded or stored, not just the opcode name.

llvm-svn: 113854

llvm-svn: 113849

llvm-svn: 113847

llvm-svn: 113846

by morphing the 'and' to its recording form 'andS'.

This is basically a test commit into this area, to
see whether the bots like me. Several generalizations
can be applied and various avenues of code simplification
are open. I'll introduce those as I go.

I am aware of stylistic input from Bill Wendling, about
where put the analysis complexity, but I am positive
that we can move things around easily and will find a
satisfactory solution.

llvm-svn: 113839

llvm-svn: 113837

This may produce warnings on MSVS, but it's better than failures.

llvm-svn: 113834

llvm-svn: 113833

This reverts commit r113632

Conflicts:

	cmake/modules/AddLLVM.cmake

llvm-svn: 113819

register allocation.  Remove the NEONPreAllocPass, which is no longer needed.
Yeah!!

llvm-svn: 113818

pseudo-instruction approach.  Change ARMExpandPseudoInsts to use a table
to record all the NEON load/store information.

llvm-svn: 113812

v8i16 is not an MMX type; put it where it belongs.

llvm-svn: 113785

llvm-svn: 113768

llvm-svn: 113766

This problem is unrelated to the recent dependency tracking change. It
seems like noone noticed the problem because I don't think anyone compiles
any target other than X86 on windows.

llvm-svn: 113727

llvm-svn: 113712

llvm-svn: 113693

llvm-svn: 113692

This fixes rdar://8408129 - pushfd and popfd get invalid instruction mnemonic errors

llvm-svn: 113690