- Feb 18, 2011
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Jakob Stoklund Olesen authored
The rewriter works almost identically to -rewriter=trivial, except it also eliminates any identity copies. This makes the new register allocators independent of VirtRegRewriter.cpp which will be going away at the same time as RegAllocLinearScan. llvm-svn: 125967
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Bill Wendling authored
llvm-svn: 125960
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Cameron Zwarich authored
llvm-svn: 125830
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Jakob Stoklund Olesen authored
llvm-svn: 125802
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Devang Patel authored
Do not lose debug info of an inlined function argument even if the argument is only used through GEPs. llvm-svn: 125794
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- Feb 17, 2011
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Jakob Stoklund Olesen authored
llvm-svn: 125789
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Jakob Stoklund Olesen authored
A local live range is live in a single basic block. If such a range fails to allocate, try to find a sub-range that would get a larger spill weight than its interference. llvm-svn: 125764
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Duncan Sands authored
the time but presumably my email got lost). Examples where the previous logic got it wrong: (1) a signed i8 multiply of 64 by 2 overflows, but the high part is zero; (2) a signed i8 multiple of -128 by 2 overflows, but the high part is all ones. llvm-svn: 125748
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Cameron Zwarich authored
llvm-svn: 125728
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Cameron Zwarich authored
llvm-svn: 125727
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Cameron Zwarich authored
llvm-svn: 125726
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- Feb 16, 2011
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Stuart Hastings authored
other getNode() methods. Radar 9002173. llvm-svn: 125665
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Eric Christopher authored
llvm-svn: 125651
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Eric Christopher authored
transformation if we can't legally create a build vector of the correct type. Check that we can make the transformation first, and add a TODO to refactor this code with similar cases. Fixes: PR9223 and rdar://9000350 llvm-svn: 125631
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Evan Cheng authored
llvm-svn: 125625
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- Feb 15, 2011
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Devang Patel authored
Ignore DBG_VALUE machine instructions while constructing instruction ranges based on location info. Machine instruction range consisting of only DBG_VALUE MIs only contributes consecutive labels in assembly output, which is harmless, and empty scope entry in DebugInfo, which confuses debugger tools. llvm-svn: 125577
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Duncan Sands authored
llvm-svn: 125563
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Evan Cheng authored
llvm-svn: 125552
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Chris Lattner authored
llvm-svn: 125537
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Jakob Stoklund Olesen authored
Simplify the spill weight calculation a bit by bypassing getApproximateInstructionCount() and using LiveInterval::getSize() directly. This changes the computed spill weights, but only by a constant factor in each function. It should not affect how spill weights compare against each other, and so it shouldn't affect code generation. llvm-svn: 125530
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- Feb 14, 2011
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Rafael Espindola authored
section. llvm-svn: 125526
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Evan Cheng authored
Fix PR8854. Track inserted copies to avoid read before write. Sorry, it's hard to reduce a sensible small test case. llvm-svn: 125523
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Chris Lattner authored
builders unhappy. llvm-svn: 125504
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Rafael Espindola authored
llvm-svn: 125490
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Chris Lattner authored
idiom. Change various clients to simplify their code. llvm-svn: 125487
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Chris Lattner authored
vector fp conversions. llvm-svn: 125482
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Chris Lattner authored
llvm-svn: 125481
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Cameron Zwarich authored
llvm-svn: 125477
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Cameron Zwarich authored
llvm-svn: 125476
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- Feb 13, 2011
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Chris Lattner authored
have their low bits set to zero. This allows us to optimize out explicit stack alignment code like in stack-align.ll:test4 when it is redundant. Doing this causes the code generator to start turning FI+cst into FI|cst all over the place, which is general goodness (that is the canonical form) except that various pieces of the code generator don't handle OR aggressively. Fix this by introducing a new SelectionDAG::isBaseWithConstantOffset predicate, and using it in places that are looking for ADD(X,CST). The ARM backend in particular was missing a lot of addressing mode folding opportunities around OR. llvm-svn: 125470
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Chris Lattner authored
generating i8 shift amounts for things like i1024 types. Add an assert in getNode to prevent this from occuring in the future, fix the buggy transformation, revert my previous patch, and document this gotcha in ISDOpcodes.h llvm-svn: 125465
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Chris Lattner authored
the shift amounts are in a suitably wide type so that we don't generate out of range constant shift amounts. This fixes PR9028. llvm-svn: 125458
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Chris Lattner authored
is narrower than the shift register. Doing an anyext provides undefined bits in the top part of the register. llvm-svn: 125457
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- Feb 12, 2011
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Nadav Rotem authored
The DAGCombiner created illegal BUILD_VECTOR operations. The patch added a check that either illegal operations are allowed or that the created operation is legal. llvm-svn: 125435
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- Feb 11, 2011
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Nadav Rotem authored
that the condition is not a vector. llvm-svn: 125398
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Nadav Rotem authored
Fix #9190 The bug happens when the DAGCombiner attempts to optimize one of the patterns of the SUB opcode. It tries to create a zero of type v2i64. This type is legal on 32bit machines, but the initializer of this vector (i64) is target dependent. Currently, the initializer attempts to create an i64 zero constant, which fails. Added a flag to tell the DAGCombiner to create a legal zero, if we require that the pass would generate legal types. llvm-svn: 125391
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- Feb 10, 2011
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Evan Cheng authored
After 3-addressifying a two-address instruction, update the register maps; add a missing check when considering whether it's profitable to commute. rdar://8977508. llvm-svn: 125259
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Jakob Stoklund Olesen authored
Loop splitting is better handled by the more generic global region splitting based on the edge bundle graph. llvm-svn: 125243
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Jakob Stoklund Olesen authored
llvm-svn: 125238
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Jakob Stoklund Olesen authored
This fixes a bug where splitSingleBlocks() could split a live range after a terminator instruction. llvm-svn: 125237
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