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  1. Feb 18, 2011
  2. Feb 17, 2011
  3. Feb 16, 2011
  4. Feb 15, 2011
  5. Feb 14, 2011
  6. Feb 13, 2011
    • Chris Lattner's avatar
      Enhance ComputeMaskedBits to know that aligned frameindexes · 46c01a30
      Chris Lattner authored
      have their low bits set to zero.  This allows us to optimize
      out explicit stack alignment code like in stack-align.ll:test4 when
      it is redundant.
      
      Doing this causes the code generator to start turning FI+cst into
      FI|cst all over the place, which is general goodness (that is the
      canonical form) except that various pieces of the code generator
      don't handle OR aggressively.  Fix this by introducing a new
      SelectionDAG::isBaseWithConstantOffset predicate, and using it
      in places that are looking for ADD(X,CST).  The ARM backend in
      particular was missing a lot of addressing mode folding opportunities
      around OR.
      
      llvm-svn: 125470
      46c01a30
    • Chris Lattner's avatar
      Revisit my fix for PR9028: the issue is that DAGCombine was · e95d1950
      Chris Lattner authored
      generating i8 shift amounts for things like i1024 types.  Add
      an assert in getNode to prevent this from occuring in the future,
      fix the buggy transformation, revert my previous patch, and
      document this gotcha in ISDOpcodes.h
      
      llvm-svn: 125465
      e95d1950
    • Chris Lattner's avatar
      when legalizing extremely wide shifts, make sure that · d5f0b114
      Chris Lattner authored
      the shift amounts are in a suitably wide type so that
      we don't generate out of range constant shift amounts.
      
      This fixes PR9028.
      
      llvm-svn: 125458
      d5f0b114
    • Chris Lattner's avatar
      fix visitShift to properly zero extend the shift amount if the provided operand · 2a720d93
      Chris Lattner authored
      is narrower than the shift register.  Doing an anyext provides undefined bits in
      the top part of the register.
      
      llvm-svn: 125457
      2a720d93
  7. Feb 12, 2011
    • Nadav Rotem's avatar
      A fix for 9165. · db2f5481
      Nadav Rotem authored
      The DAGCombiner created illegal BUILD_VECTOR operations.
      The patch added a check that either illegal operations are
      allowed or that the created operation is legal.
      
      llvm-svn: 125435
      db2f5481
  8. Feb 11, 2011
    • Nadav Rotem's avatar
      SimplifySelectOps can only handle selects with a scalar condition. Add a check · a49a02a0
      Nadav Rotem authored
      that the condition is not a vector.
      
      llvm-svn: 125398
      a49a02a0
    • Nadav Rotem's avatar
      · 18f6a334
      Nadav Rotem authored
      Fix #9190
      
      The bug happens when the DAGCombiner attempts to optimize one of the patterns
      of the SUB opcode. It tries to create a zero of type v2i64. This type is legal
      on 32bit machines, but the initializer of this vector (i64) is target dependent.
      Currently, the initializer attempts to create an i64 zero constant, which fails.
      Added a flag to tell the DAGCombiner to create a legal zero, if we require that
      the pass would generate legal types.
      
      llvm-svn: 125391
      18f6a334
  9. Feb 10, 2011
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