llvm-svn: 203778

This was leading to bad formatting, e.g.:
Before:
  f(^{
      @autoreleasepool {
        if (a) {
          g();
  }
  }
  });

After:
  f(^{
      @autoreleasepool {
        if (a) {
          g();
        }
      }
  });

llvm-svn: 203777

llvm-svn: 203776

convenient it is to imagine a world where this works, that is not C++ as
was pointed out in review. The standard even goes to some lengths to
preclude any attempt at this, for better or worse. Maybe better. =]

llvm-svn: 203775

Create a Process::ModulesDidLoad() method to handle process-related tasks, as suggested by Jim Ingham. Make JITLoader instances use this to probe only new modules for relevant JIT symbols. Also re-enable the JITLoader hooks in Process.

llvm-svn: 203774

llvm-svn: 203773

Only one instruction pair needed changing: SMULH & UMULH. The previous
code worked, but MC was doing extra work treating Ra as a valid
operand (which then got completely overwritten in MCCodeEmitter).

No behaviour change, so no tests.

llvm-svn: 203772

llvm-svn: 203771

[C++11] DWARF parser: use SmallVector<std::unique_ptr> for parsed units in DWARFContext, and delete custom destructors

llvm-svn: 203770

llvm-svn: 203769

VSX is an ISA extension supported on the POWER7 and later cores that enhances
floating-point vector and scalar capabilities. Among other things, this adds
<2 x double> support and generally helps to reduce register pressure.

The interesting part of this ISA feature is the register configuration: there
are 64 new 128-bit vector registers, the 32 of which are super-registers of the
existing 32 scalar floating-point registers, and the second 32 of which overlap
with the 32 Altivec vector registers. This makes things like vector insertion
and extraction tricky: this can be free but only if we force a restriction to
the right register subclass when needed. A new "minipass" PPCVSXCopy takes care
of this (although it could do a more-optimal job of it; see the comment about
unnecessary copies below).

Please note that, currently, VSX is not enabled by default when targeting
anything because it is not yet ready for that.  The assembler and disassembler
are fully implemented and tested. However:

 - CodeGen support causes miscompiles; test-suite runtime failures:
      MultiSource/Benchmarks/FreeBench/distray/distray
      MultiSource/Benchmarks/McCat/08-main/main
      MultiSource/Benchmarks/Olden/voronoi/voronoi
      MultiSource/Benchmarks/mafft/pairlocalalign
      MultiSource/Benchmarks/tramp3d-v4/tramp3d-v4
      SingleSource/Benchmarks/CoyoteBench/almabench
      SingleSource/Benchmarks/Misc/matmul_f64_4x4

 - The lowering currently falls back to using Altivec instructions far more
   than it should. Worse, there are some things that are scalarized through the
   stack that shouldn't be.

 - A lot of unnecessary copies make it past the optimizers, and this needs to
   be fixed.

 - Many more regression tests are needed.

Normally, I'd fix these things prior to committing, but there are some
students and other contributors who would like to work this, and so it makes
sense to move this development process upstream where it can be subject to the
regular code-review procedures.

llvm-svn: 203768

There are currently two schemes for mapping instruction operands to
instruction-format variables for generating the instruction encoders and
decoders for the assembler and disassembler respectively: a) to map by name and
b) to map by position.

In the long run, we'd like to remove the position-based scheme and use only
name-based mapping. Unfortunately, the name-based scheme currently cannot deal
with complex operands (those with suboperands), and so we currently must use
the position-based scheme for those. On the other hand, the position-based
scheme cannot deal with (register) variables that are split into multiple
ranges. An upcoming commit to the PowerPC backend (adding VSX support) will
require this capability. While we could teach the position-based scheme to
handle that, since we'd like to move away from the position-based mapping
generally, it seems silly to teach it new tricks now. What makes more sense is
to allow for partial transitioning: use the name-based mapping when possible,
and only use the position-based scheme when necessary.

Now the problem is that mixing the two sensibly was not possible: the
position-based mapping would map based on position, but would not skip those
variables that were mapped by name. Instead, the two sets of assignments would
overlap. However, I cannot currently change the current behavior, because there
are some backends that rely on it [I think mistakenly, but I'll send a message
to llvmdev about that]. So I've added a new TableGen bit variable:
noNamedPositionallyEncodedOperands, that can be used to cause the
position-based mapping to skip variables mapped by name.

llvm-svn: 203767

llvm-svn: 203766

llvm-svn: 203765

llvm-svn: 203764

llvm-svn: 203763

Support to the IAS was added to actually parse and handle the complex SO
expressions.  However, the object file lowering was not updated to compensate
for the fact that the shift operand may be an absolute expression.

When trying to assemble to an object file, the lowering would fail while
succeeding when emitting purely assembly.  Add an appropriate test.

The test case is inspired by the test case provided by Jiangning Liu who also
brought the issue to light.

llvm-svn: 203762

Add the Windows COFF ARM object file magic.  This enables the LLVM tools to
interact with COFF object files for Windows on ARM.

llvm-svn: 203761

[CMake] Enable a bunch of Xcode build settings that correspond to warnings that are for the most part enabled by default either by Clang or -Wall.

I personally build with these settings enabled all the time, and it
is clearer to see the actual warning flags (e.g., -Wuninitialized)
get passed by Xcode rather than seeing -Wno-uninitialized followed
by -Wall (the latter canceling out the former) and figuring out
what is going on.

Xcode will ignore build settings it doesn't understand, so this will
work on possibly older versions of Xcode that don't support all
of these settings.

llvm-svn: 203760

llvm-svn: 203759

llvm-svn: 203758

for use with C++11 range-based for-loops.

The gist of phase 1 is to remove the skipInstruction() and skipBundle()
methods from these iterators, instead splitting each iterator into a version
that walks operands, a version that walks instructions, and a version that
walks bundles.  This has the result of making some "clever" loops in lib/CodeGen
more verbose, but also makes their iterator invalidation characteristics much
more obvious to the casual reader. (Making them concise again in the future is a
good motivating case for a pre-incrementing range adapter!)

Phase 2 of this undertaking with consist of removing the getOperand() method,
and changing operator*() of the operand-walker to return a MachineOperand&.  At
that point, it should be possible to add range views for them that work as one
might expect.

llvm-svn: 203757

llvm-svn: 203756

llvm-svn: 203755

It should only run on Darwin systems, and only when a couple of
libraries are available.

llvm-svn: 203754

llvm-svn: 203753

An object whose machine type header value is unknown looks a bit odd but
is valid. If an object contains only machine-type-independent data, you
can leave the type field unspecified. Some files in oldname.lib are such
object files.

llvm-svn: 203752

Clang creates "clang-cl" as a symlink to (or a copy of) "clang" for the MSVC-
compatible driver. This patch is to do the same thing for "link" and "lld".

Differential Revision: http://llvm-reviews.chandlerc.com/D3066

llvm-svn: 203751

Fix PR18800. llvm intrinsic memcpy takes 5 arguments void @llvm.memcpy.p0i8.p0i8.i32(i8* <dest>, i8* <src>, i32 <len>, i32 <align>, i1 <isvolatile>).The test case incorrectly uses the old format resulting in isVolatile function in MemIntrinsic to crash during SROA transformation.Modified the test case to use correct signature of memcpy and memset.

llvm-svn: 203750

"ProcResource def is not included in the ProcResources".

Some of the machine model definitions were not added to the
processor's list used for diagnostics and error checking.

llvm-svn: 203749

<rdar://problem/7964505>

llvm-svn: 203748

This commit reworks how the thread plan's ShouldStopHere mechanism works, so that it is useful not only
for customizing "step-in" behavior (e.g. step-in doesn't step into code with no debug info), but also 
the behavior of step-in/step-out and step-over when they step out of the frame they started in.

I also added as a proof of concept of this reworking a mode for stepping where stepping out of a frame
into a frame with no debug information will continue stepping out till it arrives at a frame that does
have debug information.  This is useful when you are debugging callback based code where the callbacks
are separated from the code that initiated them by some library glue you don't care about, among other
things.

llvm-svn: 203747

llvm-svn: 203746

Avoid NULL pointer scenario found via clang's static analyzer.

llvm-svn: 203745

llvm-svn: 203744

llvm-svn: 203743

llvm-svn: 203742

const-qualified parameter type and the defined with a non-const-qualified
parameter type, the parameter is not const inside its body. Ensure that
the type we use when instantiating the body is the right one. Patch by
suyog sarda!

This is still rather unsatisfactory; it seems like it might be better to
instantiate at least the function parameters, and maybe the complete function
declaration, when we instantiate the definition for such a member function
(instead of reusing the declaration from inside the instantiated class
definition).

llvm-svn: 203741

FIXME: Get rid of invoking this.
I guess it wouldn't run on win32 due to lacking of shell support.

llvm-svn: 203740

llvm-svn: 203739