considered legal instructions.

Refs: A8.6.51 LDC, LDC2 (immediate) -- page A8-107, A8.6.58 LDR (immediate, ARM)
-- page A8-121, and A8.6.194 STR (immediate, ARM) -- page A8-395.

llvm-svn: 101524

llvm-svn: 101501

llvm-svn: 101500

llvm-svn: 101480

llvm-svn: 101478

llvm-svn: 101477

dependent analyses, and increase code size, so doing it profitably would
require more complex heuristics.

llvm-svn: 101471

callee is expected to be expanded to something else by codegen, so that
normal infinitely recursive calls are still transformed.

llvm-svn: 101468

with a fix for self-hosting

rotate CallInst operands, i.e. move callee to the back
of the operand array

the motivation for this patch are laid out in my mail to llvm-commits:
more efficient access to operands and callee, faster callgraph-construction,
smaller compiler binary

llvm-svn: 101465

llvm-svn: 101463

expression canonicalization. Its job is to print what's there, not to
make judgements about it.

llvm-svn: 101461

JIT doesn't use the MC back-end asm printer to emit labels that it uses, the
section for the MCSymbol is never set. And thus the MCSymbol for the EH label
isn't marked as "defined". Because of that, TidyLandingPads removes the needed
landing pads from the JIT output. This breaks EH for every JIT program.

This is a work-around for this limitation. We pass in the label locations
map. If the label has a non-zero value, then it was "emitted" by the JIT and
TidyLandingPads shouldn't remove that label.

A nicer solution would be to mark the MCSymbol as "used" by the JIT and not rely
upon the section being set to determine if it's defined or not.

llvm-svn: 101453

Adding support for dag combiner to promote operations for profit. This requires target specific queries. For example, x86 should promote i16 to i32 when it does not impact load folding.
x86 support is off by default. It can be enabled with -promote-16bit.

Work in progress.

llvm-svn: 101448

llvm-svn: 101446

llvm-svn: 101443

llvm-svn: 101438

llvm-svn: 101437

llvm-svn: 101434

wanted the alignment of the pointee.

llvm-svn: 101432

llvm-svn: 101429

place.

llvm-svn: 101427

ConvertToScalarInfo.

llvm-svn: 101425

llvm-svn: 101423

CanConvertToScalar/MergeInType.  Eliminate a pointless
LLVMContext argument to MergeInType.

llvm-svn: 101422

MachineLoopInfo is already available when MachineSinking runs, so the check is
free.

There is no test case because it would require a critical edge into a loop, and
CodeGenPrepare splits those. This check is just to be extra careful.

llvm-svn: 101420

am2offset.  Modified the instruction table entry and added a new test case.

llvm-svn: 101415

Use default lowering of DYNAMIC_STACKALLOC. As far as I can tell, ARM isle is doing the right thing and codegen looks correct for both Thumb and Thumb2.

llvm-svn: 101410

llvm-svn: 101405

with a fix

rotate CallInst operands, i.e. move callee to the back
of the operand array

the motivation for this patch are laid out in my mail to llvm-commits:
more efficient access to operands and callee, faster callgraph-construction,
smaller compiler binary

llvm-svn: 101397

llvm-svn: 101392

llvm-svn: 101388

llvm-svn: 101387

llvm-svn: 101385

ARM SelectDYN_ALLOC should emit a copy from SP rather than referencing SP directly. In cases where there are two dyn_alloc in the same BB it would have caused the old SP value to be reused and badness ensues. rdar://7493908

llvm is generating poor code for dynamic alloca, I'll fix that later.

llvm-svn: 101383

llvm-svn: 101382

llvm-svn: 101379

can't be static.

llvm-svn: 101377

llvm-svn: 101376

llvm-svn: 101375

in addition to the predecessor.

llvm-svn: 101374