Commits · 5d403f6bf8818415fd0425a89ece8a69fb6da155 · Roger Ferrer / llvm-epi-0.8 · GitLab

This project is archived. Its data is read-only.

Dec 21, 2018
- [X86][SSE] Auto upgrade PADDS/PSUBS intrinsics to SADD_SAT/SSUB_SAT generic intrinsics (llvm) · 5d403f6b
  Simon Pilgrim authored Dec 21, 2018
  5d403f6b
- [WebAssembly] Fix invalid machine instrs in -O0, verify in tests · b6dac89c
  Thomas Lively authored Dec 21, 2018
  b6dac89c
- AMDGPU/GlobalISel: RegBankSelect for amdgcn.wqm.vote · 3eae3c45
  Matt Arsenault authored Dec 21, 2018
  3eae3c45
- AMDGPU/GlobalISel: RegBankSelect for some fp ops · f4c21c57
  Matt Arsenault authored Dec 21, 2018
  f4c21c57
- AMDGPU/GlobalISel: Redo legality for build_vector · bee2ad71
  Matt Arsenault authored Dec 21, 2018
  bee2ad71
- [X86] Refactor hasNoCarryFlagUses and hasNoSignFlagUses in X86ISelDAGToDAG.cpp... · 54f1a7be
  Craig Topper authored Dec 21, 2018
  54f1a7be
- [X86] Add memory forms of some SETCC instructions to hasNoCarryFlagUses. · e0cff102
  Craig Topper authored Dec 21, 2018
  e0cff102
- [ARM] Complete the Thumb1 shift+and->shift+shift transforms. · b1bbd5dc
  Eli Friedman authored Dec 20, 2018
  b1bbd5dc
Dec 20, 2018
- [GlobalISel][AArch64] Add G_FCEIL to isPreISelGenericFloatingPointOpcode · a6b9c68a
  Jessica Paquette authored Dec 20, 2018
  a6b9c68a
- [MC] [AArch64] Correctly resolve ":abs_g1:3" etc. · 48397102
  Eli Friedman authored Dec 20, 2018
  48397102
- [MC] [AArch64] Support resolving fixups for abs_g0 etc. · 4648209e
  Eli Friedman authored Dec 20, 2018
  4648209e
- [X86] Auto upgrade XOP/AVX512 rotation intrinsics to generic funnel shift intrinsics (llvm) · 2a25360a
  Simon Pilgrim authored Dec 20, 2018
  2a25360a
- [BPF] Disable relocation for .BTF.ext section · 821c93d5
  Yonghong Song authored Dec 20, 2018
  821c93d5
- [Hexagon] Add patterns for funnel shifts · 30c42e2a
  Krzysztof Parzyszek authored Dec 20, 2018
  30c42e2a
- [RISCV] Properly evaluate fixup_riscv_pcrel_lo12 · eb3a64a4
  Alex Bradbury authored Dec 20, 2018
  eb3a64a4
- [X86][AVX512] Don't custom lower v16i8 rotations. · 09c08117
  Simon Pilgrim authored Dec 20, 2018
  09c08117
- [SystemZ] "Generic" vector assembler instructions shoud clobber CC · 380bece7
  Ulrich Weigand authored Dec 20, 2018
  380bece7
- [SystemZ] Make better use of VLLEZ · 44d37ae3
  Ulrich Weigand authored Dec 20, 2018
  44d37ae3
- [SystemZ] Make better use of VGEF/VGEG · 8bb46b0f
  Ulrich Weigand authored Dec 20, 2018
  8bb46b0f
- Re-land r349731 "[CodeGen][ExpandMemcmp] Add an option for allowing overlapping loads. · 36a34803
  Clement Courbet authored Dec 20, 2018
  36a34803
- [SystemZ] Make better use of VLDEB · f43b5100
  Ulrich Weigand authored Dec 20, 2018
  f43b5100
- Revert r349731 "[CodeGen][ExpandMemcmp] Add an option for allowing overlapping loads." · e22cf4d7
  Clement Courbet authored Dec 20, 2018
  e22cf4d7
- [CodeGen][ExpandMemcmp] Add an option for allowing overlapping loads. · 1bb6e1b0
  Clement Courbet authored Dec 20, 2018
  1bb6e1b0
- [PowerPC] Implement the isSelectSupported() target hook · ca8db489
  Kang Zhang authored Dec 20, 2018
  ca8db489
- [WebAssembly] Emit a splat for v128 IMPLICIT_DEF · feb18fe9
  Thomas Lively authored Dec 20, 2018
  feb18fe9
- Fix build errors introduced by r349712 on aarch64 bots. · 321bfb21
  Amara Emerson authored Dec 20, 2018
  321bfb21
- [WebAssembly] Gate unimplemented SIMD ops on flag · 8dbf29af
  Thomas Lively authored Dec 20, 2018
  8dbf29af
- AMDGPU: Make i1/i64/v2i32 and/or/xor legal · 43398837
  Matt Arsenault authored Dec 20, 2018
  43398837
- AMDGPU/GlobalISel: Fix ValueMapping tables for i1 · 8cc98bee
  Matt Arsenault authored Dec 20, 2018
  8cc98bee
- [X86] Disable custom widening of signed/unsigned add/sub saturation intrinsics... · 9ca2f560
  Craig Topper authored Dec 20, 2018
  9ca2f560
- [AArch64][GlobalISel] Implement selection og G_MERGE of two s32s into s64. · 8cb186ce
  Amara Emerson authored Dec 20, 2018
  8cb186ce
- AMDGPU/GlobalISel: RegBankSelect for fp conversions · dff33c38
  Matt Arsenault authored Dec 20, 2018
  dff33c38
- AMDGPU/GlobalISel: Legality/regbankselect for atomicrmw/atomic_cmpxchg · 36d40921
  Matt Arsenault authored Dec 20, 2018
  36d40921
- [X86] Remove TLI variable from ReplaceNodeResults. NFC · 217b3b20
  Craig Topper authored Dec 19, 2018
  217b3b20
Dec 19, 2018
- AMDGPU: Add patterns for v4i16/v4f16 -> v4i16/v4f16 bitcasts · 3931ad38
  Rhys Perry authored Dec 19, 2018
  3931ad38
- [AArch64] Improve Exynos predicates · 374ccf67
  Evandro Menezes authored Dec 19, 2018
  374ccf67
- [AArch64] Use canonical copy idiom · ff827d73
  Evandro Menezes authored Dec 19, 2018
  ff827d73
- [X86] Remove a bunch of 'else' after returns in reduceVMULWidth. NFC · d16da2b4
  Craig Topper authored Dec 19, 2018
  d16da2b4
- [GlobalISel][AArch64] Add support for @llvm.ceil · 3560e93d
  Jessica Paquette authored Dec 19, 2018
  3560e93d
- [X86] Don't match TESTrr from (cmp (and X, Y), 0) during isel. Defer to post processing · 84a00bd9
  Craig Topper authored Dec 19, 2018
  84a00bd9