callee's responsibility to sign or zero-extend the return value.  The additional
test case just checks to make sure the calls are selected (i.e., -fast-isel-abort
doesn't assert).

llvm-svn: 144047

zero-extend the constant integer encoding.  Test case provides testing for
both call parameters and materialization of i1, i8, and i16 types.

llvm-svn: 143821

llvm-svn: 143749

in a 16-bit immediate.  However, for the shorter non-legal types (i.e., i1, i8,
i16) we should not sign-extend.  This prevents us from materializing things
such as 'true' (i.e., i1 1).

llvm-svn: 143743

llvm-svn: 143739

llvm-svn: 143670

llvm-svn: 143669

llvm-svn: 143603

llvm-svn: 143559

llvm-svn: 143547

llvm-svn: 143523

llvm-svn: 143086

up.  Thus, improving the support for compares is goodness because it increases
the number of terminator instructions we can handle.  This creates many more 
opportunities for target specific fast-isel.

llvm-svn: 143079

place.  No functional change intended.

llvm-svn: 143078

llvm-svn: 143076

SelectBranch.  No functional change intended.

llvm-svn: 143072

llvm-svn: 142299

and block addresses.

llvm-svn: 140936

Encode the immediate into its 8-bit form as part of isel rather than later,
which simplifies things for mapping the encoding bits, allows the removal
of the custom disassembler decoding hook, makes the operand printer trivial,
and prepares things more cleanly for handling these in the asm parser.

rdar://10211428

llvm-svn: 140834

llvm-svn: 139636

llvm-svn: 139044

llvm-svn: 138918

llvm-svn: 138373

Refactor the SXTB, SXTH, SXTB16, UXTB, UXTH, and UXTB16 instructions to not
have an 'r' and an 'r_rot' version, but just a single version with a rotate
that can be zero. Use plain Pat<>'s for the ISel of the non-rotated version.

llvm-svn: 136225

Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate ARM MC code from target.

llvm-svn: 135636

llvm-svn: 135375

llvm-svn: 134030

sink them into MC layer.
- Added MCInstrInfo, which captures the tablegen generated static data. Chang
TargetInstrInfo so it's based off MCInstrInfo.

llvm-svn: 134021

No functional change.

Part of PR6965

llvm-svn: 132763

Add ARM fast-isel support for materializing the address of a global in cases where the global uses an indirect symbol.

rdar://9431157

llvm-svn: 132522

-verify-machineinstrs failures on several tests.

llvm-svn: 132268

llvm-svn: 132194

Rewrite fast-isel integer cast handling to handle more cases, and to be simpler and more consistent.

The practical effects here are that x86-64 fast-isel can now handle trunc from i8 to i1, and ARM fast-isel can handle many more constructs involving integers narrower than 32 bits (including loads, stores, and many integer casts).

rdar://9437928 .

llvm-svn: 132099

llvm-svn: 132073

llvm-svn: 131431

llvm-svn: 130716

llvm-svn: 130552

if it ever did it needs the def machinery.

llvm-svn: 130549

llvm-svn: 130546

Fix a rather obscure crash caused by ARM fast-isel generating code which redefines a register.
rdar://problem/9338332 .

llvm-svn: 130539