llvm-svn: 157492

First code from the Mips16 compiler. Includes trivial test program.

Patch by Reed Kotler.

llvm-svn: 157408

instruction encodings can be excluded during mips16 processing.

This revision fixes the issue raised by Jim Grosbach.

bool hasStandardEncoding() const { return !inMips16Mode(); }

When micromips is added it will be

bool StandardEncoding() const { return !inMips16Mode()&&  !inMicroMipsMode(); }

No additional testing is needed other than to assure that there is no regression
from this patch.

Patch by Reed Kotler.

llvm-svn: 157234

Patch by Reed Kotler.

llvm-svn: 156408

llvm-svn: 155031

Patch by Vladimir Medic. 

llvm-svn: 154935

llvm-svn: 153925

Patch by Vladimir Medic.

llvm-svn: 153924

them as machine instructions. Directives ".set noat" and ".set at" are now
emitted only at the beginning and end of a function except in the case where
they are emitted to enclose .cpload with an immediate operand that doesn't fit
in 16-bit field or unaligned load/stores.

Also, make the following changes:
- Remove function isUnalignedLoadStore and use a switch-case statement to
  determine whether an instruction is an unaligned load or store.

- Define helper function CreateMCInst which generates an instance of an MCInst
  from an opcode and a list of operands.

llvm-svn: 153552

any side effects.

llvm-svn: 153551

llvm-svn: 151847

llvm-svn: 151625

llvm-svn: 151615

load and store instructions.

llvm-svn: 151611

add/sub instructions.

llvm-svn: 151415

reserving a physical register ($gp or $28) for that purpose.

This will completely eliminate loads that restore the value of $gp after every
function call, if the register allocator assigns a callee-saved register, or
eliminate unnecessary loads if it assigns a temporary register. 

example:

.cpload $25       // set $gp.
...
.cprestore 16     // store $gp to stack slot 16($sp).
...
jalr $25          // function call. clobbers $gp.
lw $gp, 16($sp)   // not emitted if callee-saved reg is chosen.
...
lw $2, 4($gp)
...
jalr $25          // function call.
lw $gp, 16($sp)   // not emitted if $gp is not live after this instruction.
...

llvm-svn: 151402

llvm-svn: 148862

llvm-svn: 147519

  versions derive from them.
- JALR64 is not needed since N64 does not emit jal. 
- Add template parameter to BranchLink that sets the rt field. 
- Fix the set of temporary registers for O32 and N64.

llvm-svn: 147518

The patch and test case were originally written by Mans Rullgard.

llvm-svn: 147024

instruction supported by mips32r2, and add a pattern which replaces bswap with
a ROTR and WSBH pair.
 
WSBW is removed since it is not an instruction the current architectures
support.

llvm-svn: 147015

only when the target ABI is N64.

llvm-svn: 147001

only when the target ABI is N64. 

llvm-svn: 146992

patterns emit a single LUi instruction instead of a pair of LUi and ORi.

llvm-svn: 146900

llvm-svn: 146896

-relocation-model=static.

llvm-svn: 146432

llvm-svn: 146232

- Modify lowering of global TLS address nodes.
- Modify isel of ThreadPointer.
- Wrap target global TLS address nodes that are operands of loads with WrapperPIC. 
- Remove Mips-specific DAG nodes TlsGd, TprelHi and TprelLo, which can be
  substituted with other existing nodes.

llvm-svn: 146175

RDHWR. 

llvm-svn: 146101

llvm-svn: 146081

llvm-svn: 146059

llvm-svn: 145912

them.

llvm-svn: 145852

- lower unaligned loads/stores.
- encode the size operand of instructions INS and EXT.
- emit relocation information needed for JAL (jump-and-link).  

llvm-svn: 145113

nodes.

llvm-svn: 144841

llvm-svn: 144840

"With this patch we can now generate runnable Mips code through LLVM
direct object emission. We have run numerous simple programs, both C
and C++ and with -O0 and -O3 from the output. The code is not production
ready, but quite useful for experimentation." Patch and message by
Jack Carter

llvm-svn: 144414

llvm-svn: 144372

llvm-svn: 144370

llvm-svn: 144368