llvm-svn: 63026

markers, and ended up foiling the interval reconstruction.

This allows us to turn on reconstruction in the pre alloc splitter, which
fixes a number of miscompilations.

llvm-svn: 63025

Enhance logic in X86DAGToDAGISel::PreprocessForRMW which move load inside callseq_start to allow it to be folded into a call. It was not considering the cases where a token factor is between the load and the callseq_start.

llvm-svn: 63022

llvm-svn: 63021

llvm-svn: 63017

assignment operator) were returning a copy of the bit vector, instead of a
reference! This old semantics probably did not meet the expectations.
With this patch, chained assignments happen to the right object.

llvm-svn: 63012

llvm-svn: 63009

llvm-svn: 63008

llvm-svn: 63007

llvm-svn: 63005

has a different number of elements than the output.

llvm-svn: 62998

tidy up SDUse and related code.
 - Replace the operator= member functions with a set method, like
   LLVM Use has, and variants setInitial and setNode, which take
   care up updating use lists, like LLVM Use's does. This simplifies
   code that calls these functions.
 - getSDValue() is renamed to get(), as in LLVM Use, though most
   places can either use the implicit conversion to SDValue or the
   convenience functions instead.
 - Fix some more node vs. value terminology issues.

Also, eliminate the one remaining use of SDOperandPtr, and
SDOperandPtr itself.

llvm-svn: 62995

llvm-svn: 62991

- Rename fcmp.ll test to fcmp32.ll, start adding new double tests to fcmp64.ll
- Fix select_bits.ll test
- Capitulate to the DAGCombiner and move i64 constant loads to instruction
  selection (SPUISelDAGtoDAG.cpp).

  <rant>DAGCombiner will insert all kinds of 64-bit optimizations after
  operation legalization occurs and now we have to do most of the work that
  instruction selection should be doing twice (once to determine if v2i64
  build_vector can be handled by SelectCode(), which then runs all of the
  predicates a second time to select the necessary instructions.) But,
  CellSPU is a good citizen.</rant>

llvm-svn: 62990

llvm-svn: 62989

llvm-svn: 62988

llvm-svn: 62987

llvm-svn: 62986

llvm-svn: 62985

handling the flaw inherent in that assumption.  :)

llvm-svn: 62984

llvm-svn: 62983

llvm-svn: 62982

other x86 segments.  address space 0 is stack/default, 1-255 are reserved for
client use.

llvm-svn: 62980

llvm-svn: 62979

llvm-svn: 62976

llvm-svn: 62973

for example in the case of va-args. XFAIL associated tests.

llvm-svn: 62972

llvm-svn: 62969

llvm-svn: 62967

of each use in the SelectionDAG ReplaceAllUses* functions. Thanks
to Chris for spotting this opportunity.

Also, factor out code from all 5 of the ReplaceAllUses* functions
into AddNonLeafNodeToCSEMaps, which is now renamed
AddModifiedNodeToCSEMaps to more accurately reflect its purpose.

llvm-svn: 62964

llvm-svn: 62963

DeleteNodeNotInCSEMaps, since DeleteNode just calls
DeleteNodeNotInCSEMaps.

llvm-svn: 62962

llvm-svn: 62961

code that rounded up and capped the size.

llvm-svn: 62958

llvm-svn: 62957

llvm-svn: 62956

llvm-svn: 62955

Teach 2addr pass to be do more commuting. If both uses of a two-address instruction are killed, but the first operand has a use before and after the def, commute if the second operand does not suffer from the same issue.
%reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1                                                                                                                                     
%reg1029<def> = MOV8rr %reg1028                                                                                                                                                      
%reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>                                                                                                                            
insert => %reg1030<def> = MOV8rr %reg1028                                                                                                                                            
%reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead>                                                                                                         

In this case, it might not be possible to coalesce the second MOV8rr                                                                                                                 
instruction if the first one is coalesced. So it would be profitable to                                                                                                              
commute it:                                                                                                                                                                          
%reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1                                                                                                                                     
%reg1029<def> = MOV8rr %reg1028                                                                                                                                                      
%reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>                                                                                                                            
insert => %reg1030<def> = MOV8rr %reg1029                                                                                                                                            
%reg1030<def> = ADD8rr %reg1029<kill>, %reg1028<kill>, %EFLAGS<imp-def,dead>

llvm-svn: 62954

llvm-svn: 62940

more accurate change loses more than it gains on
benchmarks.

llvm-svn: 62938