Commits · 5ed07c03f45d18dd34731beacf4891d7f7799dd1 · Roger Ferrer / llvm-epi-0.8

Nov 12, 2011
- 64-bit arbitrary immediate pattern. · 5ed07c03
  Akira Hatanaka authored Nov 12, 2011
```
llvm-svn: 144448
```
  5ed07c03
Nov 11, 2011
- 64-bit atomic instructions. · 21cbc25b
  Akira Hatanaka authored Nov 11, 2011
```
llvm-svn: 144372
```
  21cbc25b
- Add 64-bit versions of LEA_ADDiu and DynAlloc. Modify LowerDYNAMIC_STACKALLOC. · 4bdfec57
  Akira Hatanaka authored Nov 11, 2011
```
llvm-svn: 144370
```
  4bdfec57
- 64-bit versions of jal, jalr and bal. · 0009dc20
  Akira Hatanaka authored Nov 11, 2011
```
llvm-svn: 144368
```
  0009dc20
Nov 07, 2011
- Add definition of 64-bit load upper immediate. · 2b8d1f16
  Akira Hatanaka authored Nov 07, 2011
```
llvm-svn: 143994
```
  2b8d1f16
- Fix patterns for unaligned 32-bit load. DSLL32 or DSRL32 should be emitted · cf7e5b09
  Akira Hatanaka authored Nov 07, 2011
```
when shift amount is larger than 32.

llvm-svn: 143990
```
  cf7e5b09
- Make the type of shift amount i32 in order to reduce the number of shift · 770f0646
  Akira Hatanaka authored Nov 07, 2011
```
instruction definitions.

llvm-svn: 143989
```
  770f0646
- Add 64-bit to 32-bit trunc pattern. · d5c13290
  Akira Hatanaka authored Nov 07, 2011
```
llvm-svn: 143988
```
  d5c13290
Oct 17, 2011
- Redefine count-leading 0s and 1s instructions. · 33fe8f90
  Akira Hatanaka authored Oct 17, 2011
```
llvm-svn: 142216
```
  33fe8f90
- Redefine mfhi/lo and mthi/lo instructions. · 8c446be2
  Akira Hatanaka authored Oct 17, 2011
```
llvm-svn: 142214
```
  8c446be2
- Redefine multiply and divide instructions. · 0317b653
  Akira Hatanaka authored Oct 17, 2011
```
llvm-svn: 142211
```
  0317b653
- Add definition of a base class for logical shift/rotate instructions with two · 2736bbc0
  Akira Hatanaka authored Oct 17, 2011
```
source registers and redefine 32-bit and 64-bit instructions.

llvm-svn: 142210
```
  2736bbc0
- Add definition of a base class for logical shift/rotate immediate instructions · 73081309
  Akira Hatanaka authored Oct 17, 2011
```
and have 32-bit and 64-bit instructions derive from it.

llvm-svn: 142207
```
  73081309
- Add definition of immZExt5_64 and redefine immZExt5 as an ImmLeaf. · e3f27b79
  Akira Hatanaka authored Oct 17, 2011
```
llvm-svn: 142205
```
  e3f27b79
Oct 12, 2011
- Define base class LogicNOR and make 32-bit and 64-bit NOR derive from it. · 3261c0fa
  Akira Hatanaka authored Oct 12, 2011
```
llvm-svn: 141761
```
  3261c0fa
- Define class ArithLogicI. Make 32-bit and 64-bit arithmetic and logical · 8f0d549c
  Akira Hatanaka authored Oct 11, 2011
```
instructions with two register operands derive from it.

llvm-svn: 141742
```
  8f0d549c
- Define classes ArithLogicR and ArithLogicOfR and make 32-bit and 64-bit · ae5a9d65
  Akira Hatanaka authored Oct 11, 2011
```
arithmetic and logical instructions with three register operands derive from
them. Fix instruction encoding too.

llvm-svn: 141736
```
  ae5a9d65
Oct 11, 2011
- Change the names of 64-bit logical instructions so that they match the names of · 453ac88b
  Akira Hatanaka authored Oct 11, 2011
```
the real instructions.

llvm-svn: 141718
```
  453ac88b
- Remove redundancy in setcc patterns using multiclass. · 46a7994a
  Akira Hatanaka authored Oct 11, 2011
```
llvm-svn: 141715
```
  46a7994a
- Use sltiu instead of sltu when a register operand and immediate are compared. · 8c1c5104
  Akira Hatanaka authored Oct 11, 2011
```
llvm-svn: 141708
```
  8c1c5104
- Add patterns for conditional branches with 64-bit register operands. · 7148bce8
  Akira Hatanaka authored Oct 11, 2011
```
llvm-svn: 141696
```
  7148bce8
- Add support for 64-bit set-on-less-than instructions. · f75add62
  Akira Hatanaka authored Oct 11, 2011
```
llvm-svn: 141695
```
  f75add62
- Add support for conditional branch instructions with 64-bit register operands. · 4b6ac98f
  Akira Hatanaka authored Oct 11, 2011
```
llvm-svn: 141694
```
  4b6ac98f
- Make changes necessary for supporting floating point load and store instructions · b6d72cbe
  Akira Hatanaka authored Oct 11, 2011
```
that have 64-bit pointers or access the 32 x 64-bit floating pointer register
file. Update functions in MipsInstrInfo.cpp too.

llvm-svn: 141623
```
  b6d72cbe
- Modify lowering of GlobalAddress so that correct code is emitted when target is · 09b23eb7
  Akira Hatanaka authored Oct 11, 2011
```
Mips64.

llvm-svn: 141618
```
  09b23eb7
- Add definitions of 64-bit loads and stores. Add a patterns for unaligned · be68f3c3
  Akira Hatanaka authored Oct 11, 2011
```
zextloadi32 for which there is no corresponding pseudo or real instruction. 

llvm-svn: 141608
```
  be68f3c3
- Change definitions of classes LoadM and StoreM in preparation for adding support · fd2d7dcc
  Akira Hatanaka authored Oct 11, 2011
```
for 64-bit load and store instructions. Add definitions of 64-bit memory operand
and 16-bit immediate operand.

llvm-svn: 141603
```
  fd2d7dcc
Oct 03, 2011
- Add support for 64-bit logical NOR. · c3a6357e
  Akira Hatanaka authored Oct 03, 2011
```
llvm-svn: 141029
```
  c3a6357e
- Add support for 64-bit count leading ones and zeros instructions. · 48a72ca0
  Akira Hatanaka authored Oct 03, 2011
```
llvm-svn: 141028
```
  48a72ca0
- Add support for 64-bit divide instructions. · b1538f91
  Akira Hatanaka authored Oct 03, 2011
```
llvm-svn: 141024
```
  b1538f91
- Add support for 64-bit integer multiply instructions. · a279d9bd
  Akira Hatanaka authored Oct 03, 2011
```
llvm-svn: 141017
```
  a279d9bd
- Add definitions of instructions which move values between 64-bit integer · cdcc7456
  Akira Hatanaka authored Oct 03, 2011
```
registers and 64-bit HI and LO registers. Fix encoding of the 32-bit versions
of the instructions.

llvm-svn: 141015
```
  cdcc7456
Sep 30, 2011
- Add definitions of Mips64 rotate instructions. · 7ba8a8d6
  Akira Hatanaka authored Sep 30, 2011
```
llvm-svn: 140870
```
  7ba8a8d6
- isCommutable should be 0 for DSUBu. · 9727af76
  Akira Hatanaka authored Sep 30, 2011
```
llvm-svn: 140862
```
  9727af76
- Mips64 shift instructions. · 61e256aa
  Akira Hatanaka authored Sep 30, 2011
```
llvm-svn: 140841
```
  61e256aa
- Mips64 arithmetic and logical instructions with one source register and · 7769a777
  Akira Hatanaka authored Sep 30, 2011
```
immediate.

llvm-svn: 140839
```
  7769a777
Sep 29, 2011
- Mips64 arithmetic and logical instructions with two source registers. · 36036412
  Akira Hatanaka authored Sep 29, 2011
```
llvm-svn: 140806
```
  36036412
Sep 28, 2011
- Mips64 predicate definitions. Patch by Liu. · c117967b
  Akira Hatanaka authored Sep 28, 2011
```
llvm-svn: 140703
```
  c117967b
Sep 24, 2011
- Add .td file. · 7d7ee0c3
  Akira Hatanaka authored Sep 24, 2011
```
llvm-svn: 140446
```
  7d7ee0c3
Dec 16, 2010

MC: Move target specific fixup info descriptors to TargetAsmBackend instead of · 0c9d9fdd

Daniel Dunbar authored Dec 16, 2010

the MCCodeEmitter, which seems like a better organization.
 - Also, cleaned up some magic constants while in the area.

llvm-svn: 121953

0c9d9fdd