llvm-mc gives an "invalid operand" error for instructions that take an unsigned
immediate which have the high bit set such as:
    pblendw $0xc5, %xmm2, %xmm1
llvm-mc treats all x86 immediates as signed values and range checks them.
A small number of x86 instructions use the imm8 field as a set of bits.
This change only changes those instructions and where the high bit is not
ignored.  The others remain unchanged.

llvm-svn: 136287

Use range checked immediate operands for instructions. Add tests.

llvm-svn: 136285

llvm-svn: 136283

Fix parsing of the 's' suffix for the mnemonic. Add tests.

llvm-svn: 136277

Fix parsing of the 's' suffix for the mnemonic. Add tests.

llvm-svn: 136274

Encode the width operand as it encodes in the instruction, which simplifies
the disassembler and the encoder, by using the imm1_32 operand def. Add a
diagnostic for the context-sensitive constraint that the width must be in
the range [1,32-lsb].

llvm-svn: 136264

Refactor the STRT and STRBT instructions to distinguish between the register-addend and immediate-addend versions.  Temporarily XFAIL the asm parsing tests for these instructions.

llvm-svn: 136255

This adds the new instructions 'landingpad' and 'resume'.

llvm-svn: 136253

Assembly parser handling for extend instruction rotate operands. Add tests
for the sign extend instructions.

llvm-svn: 136252

X86ISD::MEMBARRIER does not require SSE2; it doesn't actually generate any code, and all x86 processors will honor the required semantics.

llvm-svn: 136249

llvm-svn: 136229

Refactor the rest of the extend instructions to not artificially distinguish
between a rotate of zero and a rotate of any other value. Replace the by-zero
versions with Pat<>'s for ISel.

llvm-svn: 136226

Refactor the SXTB, SXTH, SXTB16, UXTB, UXTH, and UXTB16 instructions to not
have an 'r' and an 'r_rot' version, but just a single version with a rotate
that can be zero. Use plain Pat<>'s for the ISel of the non-rotated version.

llvm-svn: 136225

C++0x.

llvm-svn: 136211

llvm-svn: 136201

usage of the shuffle bitmask. Both work in 128-bit lanes without
crossing, but in the former the mask of the high part is the same
used by the low part while in the later both lanes have independent
masks. Handle this properly and and add support for vpermilpd.

llvm-svn: 136200

llvm-svn: 136199

llvm-svn: 136197

On x86 we can't encode an immediate LHS of a sub directly. If the RHS comes from a XOR with a constant we can
fold the negation into the xor and add one to the immediate of the sub. Then we can turn the sub into an add,
which can be commuted and encoded efficiently.

This code is generated for __builtin_clz and friends.

llvm-svn: 136167

different from the previous 128-bit because they work in lanes.
Update a few comments and add testcases

llvm-svn: 136157

Allow the rot_imm operand to be optional. This sets the stage for refactoring
away the "rr" versions from the multiclasses and replacing them with Pat<>s.

llvm-svn: 136154

Start of cleaning this up a bit. First step is to remove the encoder hook by
storing the operand as the bits it'll actually encode to so it can just be
directly used. Map it to the assembly source values 8/16/24 when we print it.

llvm-svn: 136152

Prevent x86-specific DAGCombine from creating nodes with illegal type (which could not be selected).  Fixes a minor isel issue that was breaking the testcase from r136130.

llvm-svn: 136148

Split am2offset into register addend and immediate addend forms, necessary for allowing the fixed-length disassembler to distinguish between SBFX and STR_PRE.

llvm-svn: 136141

llvm-svn: 136138

llvm-svn: 136132

llvm-svn: 136110

llvm-svn: 136109

llvm-svn: 136108

rdar://9842203

llvm-svn: 136102

llvm-svn: 136098

llvm-svn: 136096

No intendeded functional change. Just cleaning up a bit to make things more
self-consistent in layout and style.

llvm-svn: 136095

llvm-svn: 136091

llvm-svn: 136090

llvm-svn: 136065

llvm-svn: 136051

support for 256-bit versions (but no instruction selection yet, coming next).

llvm-svn: 136050

llvm-svn: 136049

llvm-svn: 136048