- Feb 18, 2006
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Evan Cheng authored
llvm-svn: 26272
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- Feb 17, 2006
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Chris Lattner authored
llvm-svn: 26260
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Evan Cheng authored
llvm-svn: 26259
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Nate Begeman authored
and SUBE nodes that actually expose what's going on and allow for significant simplifications in the targets. llvm-svn: 26255
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Chris Lattner authored
llvm-svn: 26253
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Jeff Cohen authored
llvm-svn: 26252
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Nate Begeman authored
llvm-svn: 26250
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Nate Begeman authored
llvm-svn: 26249
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Evan Cheng authored
issue. Need to do more experiments. llvm-svn: 26247
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Nate Begeman authored
llvm-svn: 26246
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Evan Cheng authored
llvm-svn: 26245
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Evan Cheng authored
llvm-svn: 26244
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Chris Lattner authored
other small targets that do that can be learned from. They also have the added advantage of being tested :) llvm-svn: 26243
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- Feb 16, 2006
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Evan Cheng authored
proves to be worth 20% on Ptrdist/ks. Might be related to dependency breaking support. 2. Added FsMOVAPSrr and FsMOVAPDrr as aliases to MOVAPSrr and MOVAPDrr. These are used for FR32 / FR64 reg-to-reg copies. 3. Tell reg-allocator to generate MOVSSrm / MOVSDrm and MOVSSmr / MOVSDmr to spill / restore FsMOVAPSrr and FsMOVAPDrr. llvm-svn: 26241
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Evan Cheng authored
llvm-svn: 26240
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Nate Begeman authored
and ComputeMaskedBits to match the new improved versions in instcombine. Tested against all of multisource/benchmarks on ppc. llvm-svn: 26238
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Evan Cheng authored
llvm-svn: 26234
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Duraid Madina authored
distinguish between objects and register names, now we can have stuff with names like "f84", "in6" etc etc. this should fix one or two tests llvm-svn: 26232
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Evan Cheng authored
We do not want to emit "Loop: ... brcond Out; br Loop", as it adds an extra instruction in the loop. Instead, invert the condition and emit "Loop: ... br!cond Loop; br Out. Generalize the fix by moving it from PPCDAGToDAGISel to SelectionDAGLowering. llvm-svn: 26231
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Evan Cheng authored
transfer. According to the Intel P4 Optimization Manual: Moves that write a portion of a register can introduce unwanted dependences. The movsd reg, reg instruction writes only the bottom 64 bits of a register, not to all 128 bits. This introduces a dependence on the preceding instruction that produces the upper 64 bits (even if those bits are not longer wanted). The dependence inhibits register renaming, and thereby reduces parallelism. Not to mention movaps is shorter than movss. llvm-svn: 26226
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Evan Cheng authored
Turns them into calls to memset / memcpy if 1) buffer(s) are not DWORD aligned, 2) size is not known to be greater or equal to some minimum value (currently 128). llvm-svn: 26224
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- Feb 15, 2006
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Evan Cheng authored
llvm-svn: 26222
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Chris Lattner authored
llvm-svn: 26217
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Chris Lattner authored
it, because this: .bss X: .byte 0 results in the assembler warning: "initialization in bss segment". Annoying. llvm-svn: 26204
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Chris Lattner authored
The ABI specifies that there is a register save area at the bottom of the stack, which means the actual used pointer needs to be an offset from the subtracted value. llvm-svn: 26202
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Evan Cheng authored
llvm-svn: 26197
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Evan Cheng authored
llvm-svn: 26196
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Evan Cheng authored
llvm-svn: 26193
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Evan Cheng authored
llvm-svn: 26192
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- Feb 14, 2006
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Chris Lattner authored
llvm-svn: 26186
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Chris Lattner authored
emit it (instead of .space), saving a bit of space in the .o file. For example: int foo[100]; int bar[100] = {}; when compiled with C++ or -fno-common results in shrinkage from 1160 to 360 bytes of space. The X86 backend can also do this on darwin. llvm-svn: 26185
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Evan Cheng authored
llvm-svn: 26183
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Evan Cheng authored
XMM registers were not being handled. llvm-svn: 26182
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Chris Lattner authored
llvm-svn: 26181
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Evan Cheng authored
llvm-svn: 26180
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Evan Cheng authored
llvm-svn: 26179
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Evan Cheng authored
llvm-svn: 26174
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Evan Cheng authored
llvm-svn: 26173
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Evan Cheng authored
maxStoresPerMemMove. Although the last one is not used. llvm-svn: 26172
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Evan Cheng authored
llvm-svn: 26169
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