llvm-svn: 42459

The only generated code difference is that now we call memcpy when
the size of the array is unknown. This matches GCC behavior and is
better since the run time value can be arbitrarily large.

llvm-svn: 42433

llvm-svn: 42429

llvm-svn: 42426

other than PPC64. Instead of fixing it, just remove it and fix all the
places that use it to use TargetData::getPointerSize() instead, as there
aren't very many. Most of the references were in DwarfWriter.cpp.

llvm-svn: 42419

llvm-svn: 42417

llvm-svn: 42413

destruction of compiler-created ones.

llvm-svn: 42383

- Added ability to emit cross class register copies to the BBRU scheduler.
- More aggressive backtracking.

llvm-svn: 42375

- Added MRegisterInfo::getCrossCopyRegClass() hook. For register classes where reg to reg copies are not possible, this returns another register class which registers in the specified register class can be copied to (and copy back from).
- X86 copyRegToReg() now supports copying between EFLAGS and GR32 / GR64 registers.

llvm-svn: 42372

Some assemblers do not recognize aliases pushfd, pushfq, popfd, and popfq. Just emit them as pushf and popf.

llvm-svn: 42371

llvm-svn: 42368

llvm-svn: 42348

llvm-svn: 42347

Tested with "make check"!

llvm-svn: 42346

llvm-svn: 42345

llvm-svn: 42335

llvm-svn: 42333

llvm-svn: 42332

llvm-svn: 42323

llvm-svn: 42322

llvm-svn: 42316

llvm-svn: 42313

llvm-svn: 42312

both results with a single div or idiv instruction. This uses new X86ISD
nodes for DIV and IDIV which are introduced during the legalize phase
so that the SelectionDAG's CSE can automatically eliminate redundant
computations.

llvm-svn: 42308

the check to see if the assembler supports .loc from X86TargetLowering
into the superclass TargetLowering.

llvm-svn: 42297

Added support for new condition code modeling scheme (i.e. physical register dependency). These are a bunch of instructions that are duplicated so the x86 backend can support both the old and new schemes at the same time. They will be deleted after
all the kinks are worked out.

llvm-svn: 42285

llvm-svn: 42283

llvm-svn: 42282

have situations where an SSE instruction turns into
multiple blocks, with the live range of an x87
register crossing them.  To do this correctly make
sure we examine all blocks when inserting
FP_REG_KILL.  PR 1697.  (This was exposed by my
fix for PR 1681, but the same thing could happen
mixing x87 long double with SSE.)

llvm-svn: 42281

instead of ISD::LABEL with a manual .debug_line entry when the assembler
supports .file and .loc directives.

llvm-svn: 42278

aren't really usable without each other. 

llvm-svn: 42274

Fixed some comments

llvm-svn: 42271

llvm-svn: 42268

code that creates the label too.

llvm-svn: 42265

asm to die with:

ScheduleDAG.cpp:269: failed assertion `false && "Couldn't find the register class"'

instead of:
failed assertion `RegMap->getRegClass(VReg) == RC && "Register class of operand and regclass of use don't agree!"'

yay.

llvm-svn: 42259

keep f32 in SSE registers and f64 in x87.  This
is effectively a new codegen mode.
Change addLegalFPImmediate to permit float and
double variants to do different things.
Adjust callers.

llvm-svn: 42246

llvm-svn: 42239

Implement calls to functions with byval arguments on X86

llvm-svn: 42192

llvm-svn: 42189