llvm-svn: 184792

llvm-svn: 184788

llvm-svn: 184783

never modified. No functional change.

llvm-svn: 184781

[PowerPC] Support some miscellaneous mnemonics in the asm parser

This adds support for the following extended mnemonics:
  xnop
  mr.
  not
  not.
  la

llvm-svn: 184767

llvm-svn: 184764

Representing enumerators by int64 instead of uint64 for now. At some
point we need to address the underlying issue of representation
depending on the specific enumeration.

llvm-svn: 184761

llvm-svn: 184760

llvm-svn: 184758

[PowerPC] Add some FIXMEs

A bunch of extendend mnemomics ought to support '.' forms.
Add FIXMEs to the test case for those.

llvm-svn: 184757

our -> or

llvm-svn: 184756

[PowerPC] Add predicted forms of branches

This adds support for the predicted forms of branches (+/-).
There are three cases to consider:
- Branches using a PPC::Predicate code
  For these, I've added new PPC::Predicate codes corresponding
  to the BO values for predicted branch forms, and updated insn
  printing to print them correctly.  I've also added new aliases
  for the asm parser matching the new forms.
- bt/bf
  I've added new aliases matching to gBC etc.
- bd(n)z variants
  I've added new instruction patterns for the predicted forms.

In all cases, the new patterns are used for the asm parser only.
(The new infrastructure ought to be sufficient to allow use by
the compiler too at some point.)

llvm-svn: 184754

llvm-svn: 184750

llvm-svn: 184749

All of LLVM's Python scripts only support Python 2 for widely understood
reasons.

Patch by Yonggang Luo.

llvm-svn: 184732

llvm-svn: 184731

llvm-svn: 184730

llvm-svn: 184729

NVPTXTargetObjectFile.h: Initialize some pointers as NULL in the constructor of NVPTXTargetObjectFile. ~NVPTXTargetObjectFile() tries to delete them.

It caused crash on some hosts since r184595.

llvm-svn: 184728

[PowerPC] Add t/f branch mnemonics to asm parser

This adds the bt/bf/bd(n)zt/bd(n)zf mnemonics as aliases for the
asm parser, resolving to the generic conditional patterns.

llvm-svn: 184725

This should hopefully have fixed the stage2/stage3 miscompare on the dragonegg
testers.

"LoopVectorize: Use the dependence test utility class

We now no longer need alias analysis - the cases that alias analysis would
handle are now handled as accesses with a large dependence distance.

We can now vectorize loops with simple constant dependence distances.

  for (i = 8; i < 256; ++i) {
    a[i] = a[i+4] * a[i+8];
  }

  for (i = 8; i < 256; ++i) {
    a[i] = a[i-4] * a[i-8];
  }

We would be able to vectorize about 200 more loops (in many cases the cost model
instructs us no to) in the test suite now. Results on x86-64 are a wash.

I have seen one degradation in ammp. Interestingly, the function in which we
now vectorize a loop is never executed so we probably see some instruction
cache effects. There is a 2% improvement in h264ref. There is one or the other
TSCV loop kernel that speeds up.

radar://13681598"

llvm-svn: 184724

We are creating the runtime checks using this set so we need a deterministic
iteration order.

llvm-svn: 184723

[PowerPC] Support generic conditional branches in asm parser

This adds instruction patterns to cover the generic forms of
the conditional branch instructions.  This allows the assembler
to support the generic mnemonics.

The compiler will still generate the various specific forms
of the instruction that were already supported.

llvm-svn: 184722

[PowerPC] Support absolute branches

There is currently only limited support for the "absolute" variants
of branch instructions.  This patch adds support for the absolute
variants of all branches that are currently otherwise supported.

This requires adding new fixup types so that the correct variant
of relocation type can be selected by the object writer.

While the compiler will continue to usually choose the relative
branch variants, this will allow the asm parser to fully support
the absolute branches, with either immediate (numerical) or
symbolic target addresses.

No change in code generation intended.

llvm-svn: 184721

[PowerPC] Support bd(n)zl and bd(n)zlrl

This adds support for the bd(n)zl and bd(n)zlrl instructions.
The patterns are currently used for the asm parser only.

llvm-svn: 184720

[PowerPC] Support b(cond)l in the asm parser

This patch adds support for the conditional variants of bl.
The pattern is currently used by the asm parser only.

llvm-svn: 184719

[PowerPC] Support blrl and variants in the asm parser

This patch adds support for blrl and its conditional variants.
The patterns are (currently) used for the asm parser only.

llvm-svn: 184718

 This patch introduces RegisterOperand class into Mips FPU instruction definitions and adds dedicated parser methods to MipsAsmParser. It is the first in a series of patches that should fix the problems with parsing Mips FPU instructions and optimize the code in MipsAsmParser.

llvm-svn: 184716

llvm-svn: 184715

[APFloat] Added a large unittest for APFloat.add that checks that special values are computed correctly.

llvm-svn: 184714

llvm-svn: 184713

llvm-svn: 184712

[APFloat] Removed a assert from significandParts() which says that one can only access the significand of FiniteNonZero/NaN floats.

The method significandParts() is a helper method meant to ease access to
APFloat's significand by allowing the user to not need to be aware of whether or
not the APFloat is using memory allocated in the instance itself or in an
external array.

This assert says that one can only access the significand of FiniteNonZero/NaN
floats. This makes it cumbersome and more importantly dangerous when one wishes
to zero out the significand of a zero/infinity value since one will have to deal
with the aforementioned quandary related to how the memory in APFloat is
allocated.

llvm-svn: 184711

[APFloat] Rename macro convolve => PackCategoriesIntoKey so that it is clear what APFloat is actually using said macro for.

In the context of APFloat, seeing a macro called convolve suggests that APFloat
is using said value in some sort of convolution somewhere in the source code.
This is misleading.

I also added a documentation comment to the macro.

llvm-svn: 184710

llvm-svn: 184709

When encoded to thumb, VFP instruction and VMOV/VDUP between scalar and
core registers, must have their predicate bit to 0b1110.

llvm-svn: 184707

llvm-svn: 184706

Sorry for the unit test churn. I'll try to make the change permanently
next time.

llvm-svn: 184705

In thumb1, NOP is a pseudo-instruction equivalent to mov r8, r8.
However the disassembler should not use this alias.

llvm-svn: 184703

mask == 0 -> UNPRED

llvm-svn: 184702