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  1. Apr 06, 2013
    • Tom Stellard's avatar
      R600: Add RV670 processor · 60174bb9
      Tom Stellard authored
      
      
      This is an R600 GPU with double support.
      
      Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
      llvm-svn: 178929
      60174bb9
    • Tom Stellard's avatar
      R600/SI: Add processor types for each SI variant · 2f21c7e5
      Tom Stellard authored
      
      
      Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
      llvm-svn: 178928
      2f21c7e5
    • Tom Stellard's avatar
      R600/SI: Avoid generating S_MOVs with 64-bit immediates v2 · edbf1eb4
      Tom Stellard authored
      
      
      SITargetLowering::analyzeImmediate() was converting the 64-bit values
      to 32-bit and then checking if they were an inline immediate.  Some
      of these conversions caused this check to succeed and produced
      S_MOV instructions with 64-bit immediates, which are illegal.
      
      v2:
        - Clean up logic
      
      Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
      llvm-svn: 178927
      edbf1eb4
    • Hal Finkel's avatar
      Enable early if conversion on PPC · ed6a2859
      Hal Finkel authored
      On cores for which we know the misprediction penalty, and we have
      the isel instruction, we can profitably perform early if conversion.
      This enables us to replace some small branch sequences with selects
      and avoid the potential stalls from mispredicting the branches.
      
      Enabling this feature required implementing canInsertSelect and
      insertSelect in PPCInstrInfo; isel code in PPCISelLowering was
      refactored to use these functions as well.
      
      llvm-svn: 178926
      ed6a2859
    • Hal Finkel's avatar
      Correct the PPC A2 misprediction penalty · 85526f2e
      Hal Finkel authored
      The manual states that there is a minimum of 13 cycles from when the
      mispredicted branch is issued to when the correct branch target is
      issued.
      
      llvm-svn: 178925
      85526f2e
    • Greg Clayton's avatar
      Added support "__attribute__((__vector_size__(B)))" and "__attribute__((ext_vector_type(N)))". · 1c8ef476
      Greg Clayton authored
      Now we can:
      1 - see the return value for functions that return types that use the "ext_vector_size"
      2 - dump values that use the vector attributes ("expr $ymm0")
      3 - modified the DWARF parser to correctly parse GNU vector types from the DWARF by turning them into clang::Type::ExtVector types instead of just standard arrays
      
      llvm-svn: 178924
      1c8ef476
    • Richard Trieu's avatar
      When -Woverloaded-virtual is triggered, call HandleFunctionTypeMismatch to add · 05c4d023
      Richard Trieu authored
      more information to the notes.  This information is already present on other
      diagnostic messages that involves overloads.
      
      llvm-svn: 178923
      05c4d023
    • Michael Gottesman's avatar
      An objc_retain can serve as a use for a different pointer. · 31ba23aa
      Michael Gottesman authored
      This is the counterpart to commit r160637, except it performs the action
      in the bottomup portion of the data flow analysis.
      
      llvm-svn: 178922
      31ba23aa
    • Michael Gottesman's avatar
      Properly model precise lifetime when given an incomplete dataflow sequence. · 1d8d2577
      Michael Gottesman authored
      The normal dataflow sequence in the ARC optimizer consists of the following
      states:
      
          Retain -> CanRelease -> Use -> Release
      
      The optimizer before this patch stored the uses that determine the lifetime of
      the retainable object pointer when it bottom up hits a retain or when top down
      it hits a release. This is correct for an imprecise lifetime scenario since what
      we are trying to do is remove retains/releases while making sure that no
      ``CanRelease'' (which is usually a call) deallocates the given pointer before we
      get to the ``Use'' (since that would cause a segfault).
      
      If we are considering the precise lifetime scenario though, this is not
      correct. In such a situation, we *DO* care about the previous sequence, but
      additionally, we wish to track the uses resulting from the following incomplete
      sequences:
      
        Retain -> CanRelease -> Release   (TopDown)
        Retain <- Use <- Release          (BottomUp)
      
      *NOTE* This patch looks large but the most of it consists of updating
      test cases. Additionally this fix exposed an additional bug. I removed
      the test case that expressed said bug and will recommit it with the fix
      in a little bit.
      
      llvm-svn: 178921
      1d8d2577
    • Jason Molenda's avatar
      Reorder the Platform plugin settings so that they're now · 3b59f5c8
      Jason Molenda authored
      platform.plugin.darwin-kernel.kext-directories
      platform.plugin.darwin-kernel.search-locally-for-kexts
      
      and fix a few FileSpec handling issues for the kext-directories setting.
      
      llvm-svn: 178920
      3b59f5c8
    • Hal Finkel's avatar
      Reapply r178845 with fix - Fix bug in PEI's virtual-register scavenging · 3005c299
      Hal Finkel authored
      This fixes PEI as previously described, but correctly handles the case where
      the instruction defining the virtual register to be scavenged is the first in
      the block. Arnold provided me with a bugpoint-reduced test case, but even that
      seems too large to use as a regression test. If I'm successful in cleaning it
      up then I'll commit that as well.
      
      Original commit message:
      
          This change fixes a bug that I introduced in r178058. After a register is
          scavenged using one of the available spills slots the instruction defining the
          virtual register needs to be moved to after the spill code. The scavenger has
          already processed the defining instruction so that registers killed by that
          instruction are available for definition in that same instruction. Unfortunately,
          after this, the scavenger needs to iterate through the spill code and then
          visit, again, the instruction that defines the now-scavenged register. In order
          to avoid confusion, the register scavenger needs the ability to 'back up'
          through the spill code so that it can again process the instructions in the
          appropriate order. Prior to this fix, once the scavenger reached the
          just-moved instruction, it would assert if it killed any registers because,
          having already processed the instruction, it believed they were undefined.
      
          Unfortunately, I don't yet have a small test case. Thanks to Pranav Bhandarkar
          for diagnosing the problem and testing this fix.
      
      llvm-svn: 178919
      3005c299
    • Michael J. Spencer's avatar
      Revert "Correctly pass ownership of MemoryBuffers." · e6d5609d
      Michael J. Spencer authored
      llvm-svn: 178918
      e6d5609d
  2. Apr 05, 2013
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