MSVS2k8 doesn't define __i386__, hence all the CPU detection code was disabled.
Enable it by looking for _MSC_VER.

llvm-svn: 91217

defined in the test, and I don't have time tonight to figure it out.

llvm-svn: 91209

supported by emitGlobals, but I don't have a test case for that.

llvm-svn: 91208

just issues an error for the moment. The front end won't yet generate these
intrinsics for ARM, so this is behind the scenes until complete.

llvm-svn: 91200

While scanning through the uses of an alloca, keep track of the current offset
relative to the start of the alloca, and check memory references to see if
the offset & size correspond to a component within the alloca.  This has the
nice benefit of unifying much of the code from isSafeUseOfAllocation,
isSafeElementUse, and isSafeUseOfBitCastedAllocation.  The code to rewrite
the uses of a promoted alloca, after it is determined to be safe, is
reorganized in the same way.

Also, when rewriting GEP instructions, mark them as "in-bounds" since all the
indices are known to be safe.

llvm-svn: 91184

a vector type.

llvm-svn: 91181

Based on the patch by Brian Lucas!

llvm-svn: 91175

branches only to a landing pad. Without this check, the compiler would go into
an infinite loop because the branch to a landing pad is an "abnormal" edge which
wasn't being taken into account.

This is the meat of that fix:

  if (!PrevBB.canFallThrough() && !MBB->BranchesToLandingPad(MBB)) {

The other stuff is simplification of the "branches to a landing pad" code.

llvm-svn: 91161

llvm-svn: 91159

llvm-svn: 91158

memory barrier instructions by definition have side effects. This prevents the post-RA scheduler from moving them around.

llvm-svn: 91150

avoid spurious failures. This fixes PR5758.

llvm-svn: 91147

aggregate return values. This fixes PR5754.

llvm-svn: 91145

This is used in some weird cases like general dynamic TLS model.
This fixes PR5723

llvm-svn: 91144

llvm-svn: 91143

llvm-svn: 91140

build bots.

llvm-svn: 91113

has the 'nest' attribute.

llvm-svn: 91109

llvm-svn: 91104

llvm-svn: 91103

- Loosen the restrictions when checking of it branches to a landing pad.
- Make the loop more efficient by checking the '.insert' return value.
- Do cheaper checks first.

llvm-svn: 91101

more than one successor. Normally, these extra successors are dead. However,
some of them may branch to exception handling landing pads. If we remove those
successors, then the landing pads could go away if all predecessors to it are
removed. Before, it was checking if the direct successor was the landing
pad. But it could be the result of jumping through multiple basic blocks to get
to it. If we were to only check for the existence of an EH_LABEL in the basic
block and not remove successors if it's in there, then it could stop actually
dead basic blocks from being removed.

llvm-svn: 91092

llvm-svn: 91090

If VariableDIe is not created (may be because global was optimzed away) then do not try to use the variable die.

llvm-svn: 91077

It's not safe to coalesce a move where src and dst registers have different subregister indices. e.g.:
%reg16404:1<def> = MOV8rr %reg16412:2<kill>

llvm-svn: 91061

Create global variable DIEs after creating subprogram DIEs. This allows function level static variable's to find their context at the time of DIE creation.

llvm-svn: 91055

llvm-svn: 91053

llvm-svn: 91051

The coalescer is supposed to clean these up, but when setting up parameters
for a function call, there may be copies to physregs. If the defining
instruction has been LICM'ed far away, the coalescer won't touch it.

The register allocation hint does not always work - when the register
allocator is backtracking, it clears the hints.

This patch is more conservative than r90502, and does not break
483.xalancbmk/i686. It still breaks the PowerPC bootstrap, so it is disabled
by default, and can be enabled with the -trivial-coalesce-ends option.

llvm-svn: 91049

This code was crashing always with oprofile enabled, since it tried to create a StringRef
out of NULL, which run strlen on NULL.

llvm-svn: 91046

of the loop. We could get to this condition via indirect
branches.

llvm-svn: 91009

value size.  This only manifested when memdep inprecisely returns clobber,
which is do to a caching issue in the PR5744 testcase.  We can 'efficiently
emulate' this by using '-no-aa'

llvm-svn: 91004

Add memory barrier intrinsic support for ARM. Moving towards adding the atomic operations intrinsics.

llvm-svn: 91003

llvm-svn: 90999

llvm-svn: 90990

vector_shuffle (scalar_to_vector (i32 load (ptr + 4))), undef, <0, 0, 0, 0>
=>
vector_shuffle (v4i32 load ptr), undef, <1, 1, 1, 1>

iff ptr is 16-byte aligned (or can be made into 16-byte aligned).

llvm-svn: 90984

currently somewhat convenient for them to have the same value.

llvm-svn: 90980

llvm-svn: 90979

clobbers to forward pieces of large stores to small loads, we need to consider
the properly phi translated pointer in the store block.

llvm-svn: 90978

implicitly constant folds.

llvm-svn: 90977