llvm-svn: 47874

PPC-64 doesn't work.) This also lowers the spilling of the CR registers so that
it uses a register other than the default R0 register (the scavenger scrounges
for one). A significant part of this patch fixes how kill information is
handled.

llvm-svn: 47863

llvm-svn: 47828

llvm-svn: 47827

llvm-svn: 47826

llvm-svn: 47760

that instruction as its "last use". This fixes PR1925.

llvm-svn: 47758

llvm-svn: 47735

llvm-svn: 47711

llvm-svn: 47698

and was causing aborts with the new APInt changes. This may also be
fixing an obscure ppc64 bug.

llvm-svn: 47692

llvm-svn: 47687

llvm-svn: 47677

Don't track max alignment during stack object allocations since they can be deleted later. Let PEI compute it.

llvm-svn: 47668

stack slot and store if the  SINT_TO_FP is actually legal.  This allows
us to compile:

double a(double b) {return (unsigned)b;}

to:

_a:
	cvttsd2siq	%xmm0, %rax
	movl	%eax, %eax
	cvtsi2sdq	%rax, %xmm0
	ret

instead of:

_a:
	subq	$8, %rsp
	cvttsd2siq	%xmm0, %rax
	movl	%eax, %eax
	cvtsi2sdq	%rax, %xmm0
	addq	$8, %rsp
	ret

crazy.

llvm-svn: 47660

_test:
	movl	%edi, %eax
	ret

instead of:

_test:
        movl    $4294967295, %ecx
        movq    %rdi, %rax
        andq    %rcx, %rax
        ret

It would be great to write this as a Pat pattern that used subregs 
instead of a 'pseudo' instruction, but I don't know how to do that
in td files.

llvm-svn: 47658

llvm-svn: 47657

llvm-svn: 47644

llvm-svn: 47623

llvm-svn: 47612

try to simplify them.

llvm-svn: 47610

also fixes cfrac, flops, and 175.vpr

llvm-svn: 47605

Really feed llvm-as with the testcase, do not let it read from stdin. This fixes the hangs seen on solaris10.

llvm-svn: 47604

vr1 = extract_subreg vr2, 3
...
vr3 = extract_subreg vr1, 2
The end result is vr3 is equal to vr2 with subidx 2.

llvm-svn: 47592

after legalize.  Just because a constant is legal (e.g. 0.0 in SSE) 
doesn't mean that its negated value is legal (-0.0).  We could make
this stronger by checking to see if the negated constant is actually
legal post negation, but it doesn't seem like a big deal.

llvm-svn: 47591

operands into inline asm block.

llvm-svn: 47589

for CellSPU modifications:

- SPUInstrInfo.td refactoring: "multiclass" really is _your_ friend.
- Other improvements based on refactoring effort in SPUISelLowering.cpp,
  esp. in SPUISelLowering::PerformDAGCombine(), where zero amount shifts and
  rotates are now eliminiated, other scalar-to-vector-to-scalar silliness
  is also eliminated.
- 64-bit operations are being implemented, _muldi3.c gcc runtime now
  compiles and generates the right code. More work still needs to be done.

llvm-svn: 47532

llvm-svn: 47529

llvm-svn: 47527

llvm-svn: 47525

llvm-svn: 47513

llvm-svn: 47501

llvm-svn: 47476

instead of with mmx registers.  This horribleness is apparently
done by gcc to avoid having to insert emms in places that really 
should have it.  This is the second half of rdar://5741668.

llvm-svn: 47474

GCC apparently does this, and code depends on not having to do
emms when this happens.  This is x86-64 only so far, second half
should handle x86-32.

rdar://5741668

llvm-svn: 47470

any, we force sdisel to do all regalloc for an asm.  This
leads to gross but correct codegen.

This fixes the rest of PR2078.

llvm-svn: 47454

llvm-svn: 47432

llvm-svn: 47427

inline asms.

Fix PR2078 by marking aliases of registers used when a register is 
marked used.  This prevents EAX from being allocated when AX is listed
in the clobber set for the asm.

llvm-svn: 47426

llvm-svn: 47355