llvm-svn: 55594

llvm-svn: 55593

llvm-svn: 55591

llvm-svn: 55590

llvm-svn: 55588

instructions in CellSPU as "Expand" so that they won't be generated. I added a
"FIXME" so that this hack can be addressed and reverted once ISD::ROTR is
supported in the .td files.

llvm-svn: 55582

Dale, Could you please review this?

llvm-svn: 55581

llvm-svn: 55565

For now, can't mark XOR64rr isAsCheapAsAMove. It's technically correct. But various passes cannot handle remating these.

llvm-svn: 55562

Transform (x << (y&31)) -> (x << y). This takes advantage of the fact x86 shift instructions 2nd operand (shift count) is limited to 0 to 31 (or 63 in the x86-64 case).

llvm-svn: 55558

llvm-svn: 55554

llvm-svn: 55553

llvm-svn: 55552

llvm-svn: 55548

llvm-svn: 55546

llvm-svn: 55545

llvm-svn: 55533

llvm-svn: 55531

llvm-svn: 55530

llvm-svn: 55528

llvm-svn: 55521

llvm-svn: 55518

llvm-svn: 55512

llvm-svn: 55511

llvm-svn: 55504

In lowering SELECT_CC, removed cases where we can't flip the true and false when the compare value has a NaN

llvm-svn: 55499

llvm-svn: 55486

llvm-svn: 55478

llvm-svn: 55466

ATOMIC_LOAD_ADD_{8,16,32,64} instead of ATOMIC_LOAD_ADD.
Increased the Hardcoded Constant OpActionsCapacity to match.
Large but boring; no functional change.

This is to support partial-word atomics on ppc; i8 is
not a valid type there, so by the time we get to lowering, the
ATOMIC_LOAD nodes looks the same whether the type was i8 or i32.
The information can be added to the AtomicSDNode, but that is the
largest SDNode; I don't fully understand the SDNode allocation,
but it is sensitive to the largest node size, so increasing
that must be bad.  This is the alternative.

llvm-svn: 55457

SSE2 registers as well as the MMX registers.

llvm-svn: 55436

64-bit registers from 16-bit and smaller memory locations, prefer
instructions that define the entire 64-bit register, to avoid
partial-register updates.

llvm-svn: 55422

llvm-svn: 55394

llvm-svn: 55377

was inserted or not.  This allows bitcast in fast isel to properly handle the case
where an appropriate reg-to-reg copy is not available.

llvm-svn: 55375

assign it to a version of the xmm register with the regclass that matches its
type.  This fixes PR2715, a bug handling some crazy xpcom case in mozilla.

llvm-svn: 55358

llvm-svn: 55348

binary primitives.

llvm-svn: 55343

llvm-svn: 55341

Try approach to moving call address load inside of callseq_start. Now it's done during the preprocess of x86 isel. callseq_start's chain is changed to load's chain node; while load's chain is the last of callseq_start or the loads or copytoreg nodes inserted to move arguments to the right spot.

llvm-svn: 55338