Commits · 624eb2af6f38736de128d3a94da4c1ab8dbd8c77 · Roger Ferrer / llvm-epi-0.8 · GitLab

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Nov 16, 2011
- Disable the assertion again. Looks like fastisel is still generating bad kill markers. · 624eb2af
  Evan Cheng authored Nov 16, 2011
  624eb2af
- ARM mode aliases for bitwise instructions w/ register operands. · abcac568
  Jim Grosbach authored Nov 16, 2011
  abcac568
- Fix tablegen warning: hasSideEffects is inferred for eh_sjlj_dispatchsetup. · 0ca7ce38
  Bob Wilson authored Nov 16, 2011
  0ca7ce38
- lib/Target/ARM/CMakeLists.txt: Disable optimization in ARMISelLowering.cpp... · b345060a
  NAKAMURA Takumi authored Nov 16, 2011
  b345060a
- Sink codegen optimization level into MCCodeGenInfo along side relocation model · ecb2908b
  Evan Cheng authored Nov 16, 2011
  ecb2908b
- Record landing pads with a SmallSetVector to avoid multiple entries. · cca9aa58
  Bob Wilson authored Nov 16, 2011
  cca9aa58
- Fix the execution domain on a bunch of SSE/AVX instructions. · 3ed7d9ee
  Craig Topper authored Nov 16, 2011
  3ed7d9ee
- Update the SP in the SjLj jmpbuf whenever it changes. <rdar://problem/10444602 > · 643e63c4
  Bob Wilson authored Nov 16, 2011
  643e63c4
- Fix ARM SjLj-EH dispatch setup code. <rdar://problem/10444602 > · f6d1728d
  Bob Wilson authored Nov 16, 2011
  f6d1728d
- Remove code to enable execution dependency fix pass on VR256. VR128 is sufficient after r144636. · 07d8b5e2
  Craig Topper authored Nov 16, 2011
  07d8b5e2
- Revert r144568 now that r144730 has fixed the fast-isel kill marker bug. · 4ac36c8e
  Evan Cheng authored Nov 16, 2011
  4ac36c8e
- Merge isObjectPointerWithTrustworthySize with getPointerSize. Use it when · c7f1e799
  Nick Lewycky authored Nov 16, 2011
  c7f1e799
- If the 2addr instruction has other kills, don't move it below any other uses... · b8c55a53
  Evan Cheng authored Nov 16, 2011
  b8c55a53
- RescheduleKillAboveMI() must backtrack to before the rescheduled DBG_VALUE... · 59f8156e
  Evan Cheng authored Nov 16, 2011
  59f8156e
- Process all uses first before defs to accurately capture register liveness. rdar://10449480 · 9ddd69a8
  Evan Cheng authored Nov 16, 2011
  9ddd69a8
- CONCAT_VECTORS can have more than two operands. PR11389. · 87f92512
  Eli Friedman authored Nov 16, 2011
  87f92512
- Add a couple asserts so it will be easier to debug if we accidentally pass... · d257a464
  Eli Friedman authored Nov 16, 2011
  d257a464
- AddressSanitizer, first commit (compiler module only) · 6e6b03ec
  Kostya Serebryany authored Nov 16, 2011
  6e6b03ec
- test commit to verify that commit access works (added blank line) · db999c01
  Kostya Serebryany authored Nov 16, 2011
  db999c01
- Rename MVT::untyped to MVT::Untyped to match similar nomenclature. · ca2f78a9
  Owen Anderson authored Nov 16, 2011
  ca2f78a9
- Fix SCEV overly optimistic back edge taken count for multi-exit loops. · 90c7a108
  Andrew Trick authored Nov 16, 2011
  90c7a108
- Add FIXME comment. · af13d767
  Chad Rosier authored Nov 16, 2011
  af13d767
- Enable -widen-vmovs by default. · 653183fd
  Jakob Stoklund Olesen authored Nov 15, 2011
  653183fd
- Stabilize the output of the dwarf accelerator tables. Fixes a comparison · 0abbd0ef
  Eric Christopher authored Nov 15, 2011
  0abbd0ef
- GEPs with all zero indices are trivially coalesced by fast-isel. For example, · 291ce47d
  Chad Rosier authored Nov 15, 2011
  291ce47d
- ARM assembly parsing for register range syntax for VLD/VST register lists. · e891fe8d
  Jim Grosbach authored Nov 15, 2011
  e891fe8d
Nov 15, 2011
- ARM assembly parsing for data type suffices on NEON VMOV aliases. · 003cea60
  Jim Grosbach authored Nov 15, 2011
  003cea60
- Fix MSVC warnings by adding a cast. · 51f71054
  Nadav Rotem authored Nov 15, 2011
  51f71054
- AVX: Add support for vbroadcast from BUILD_VECTOR and refactor some of the vbroadcast code. · 37010002
  Nadav Rotem authored Nov 15, 2011
  37010002
- ARM assembly parsing two operand forms for shift instructions. · 75fb4abc
  Jim Grosbach authored Nov 15, 2011
  75fb4abc
- ARM VFP assembly parsing for VADD and VSUB two-operand forms. · a0103370
  Jim Grosbach authored Nov 15, 2011
  a0103370
- ARM accept an immediate offset in memory operands w/o the '#'. · 8279c182
  Jim Grosbach authored Nov 15, 2011
  8279c182
- Added custom lowering for load->dec->store sequence in x86 when the EFLAGS registers is used · 7c7ba1ba
  Pete Cooper authored Nov 15, 2011
  7c7ba1ba
- ARM enclosing curly braces optional on one-register VLD/VST instruction lists. · 8d579230
  Jim Grosbach authored Nov 15, 2011
  8d579230
- ARM size suffix on VFP single-precision 'vmov' is optional. · 84f0ba57
  Jim Grosbach authored Nov 15, 2011
  84f0ba57
- Insert modified DBG_VALUE into LiveDbgValueMap. · 43bde96a
  Devang Patel authored Nov 15, 2011
  43bde96a
- Fix typo. · a92a5d85
  Jim Grosbach authored Nov 15, 2011
  a92a5d85
- ARM alternate size suffices for VTRN instructions. · 131b45e6
  Jim Grosbach authored Nov 15, 2011
  131b45e6
- Fix a misplaced paren bug. · 05060f07
  Owen Anderson authored Nov 15, 2011
  05060f07
- ARM assembly parsing for optional datatype suffix on VFP VMOV GPR<->VFP insns. · 5803f6d5
  Jim Grosbach authored Nov 15, 2011
  5803f6d5