defs or uses. The regular def and use checking below covers them, and
can be more precise. It's safe to hoist an instruction with a dead
implicit def if the register isn't live into the loop header.

llvm-svn: 97352

llvm-svn: 97310

llvm-svn: 97295

for alignment into the LSDA. If the TType base offset is emitted, then put the
padding there. Otherwise, put it in the call site table length. There will be no
conflict between the two sites when placing the padding in one place.

llvm-svn: 97277

llvm-svn: 97269

The PowerPC floating point registers can represent both f32 and f64 via the
two register classes F4RC and F8RC. F8RC is considered a subclass of F4RC to
allow cross-class coalescing. This coalescing only affects whether registers
are spilled as f32 or f64.

Spill slots must be accessed with load/store instructions corresponding to the
class of the spilled register. PPCInstrInfo::foldMemoryOperandImpl was looking
at the instruction opcode which is wrong.

X86 has similar floating point register classes, but doesn't try to fold
memory operands, so there is no problem there.

llvm-svn: 97262

llvm-svn: 97261

as X86 is currently the only FastISel target.  Per review.

llvm-svn: 97255

llvm-svn: 97235

llvm-svn: 97200

the alignment requirement, if it no longer makes the TType base offset overflow
into extra bytes, then we need to pad to those bytes ourselves.

llvm-svn: 97196

llvm-svn: 97193

llvm-svn: 97192

will eliminate the need for padding in the "Call site table length". E.g., if
we have this:

    GCC_except_table1:
    Lexception1:
        .byte   0xff  ## @LPStart Encoding = omit
        .byte   0x9b  ## @TType Encoding = indirect pcrel sdata4
        .byte   0x7f  ## @TType base offset
        .byte   0x03  ## Call site Encoding = udata4
        .byte   0x89  ## Call site table length

with padding of 1. We want to emit the padding like this:
 
    GCC_except_table1:
    Lexception1:
        .byte   0xff  ## @LPStart Encoding = omit
        .byte   0x9b  ## @TType Encoding = indirect pcrel sdata4
        .byte   0xff  ## @TType base offset
        .space  1,0   ## Padding
        .byte   0x03  ## Call site Encoding = udata4
        .byte   0x89  ## Call site table length

and not with padding on the "Call site table length" entry.

llvm-svn: 97183

llvm-svn: 97169

operands are themselves vectors. Based on a patch by
Micah Villmow for PR6338.

llvm-svn: 97165

terms of store and load, which means bitcasting between scalar
integer and vector has endian-specific results, which undermines
this whole approach.

llvm-svn: 97137

llvm-svn: 97087

GCC_except_table label but before the Lexception, which the FDE references.
This causes problems as the FDE does not point to the start of an LSDA chunk.

Use an unnormalized uleb128 for the call-site table length that includes the
padding.

llvm-svn: 97078

llvm-svn: 97072

the number of value bits, not the number of bits of allocation for in-memory
storage.

Make getTypeStoreSize and getTypeAllocSize work consistently for arrays and
vectors.

Fix several places in CodeGen which compute offsets into in-memory vectors
to use TargetData information.

This fixes PR1784.

llvm-svn: 97064

more elegant.

llvm-svn: 97059

llvm-svn: 97057

Use a SmallPtrSet as suggested by Chris.

llvm-svn: 97056

the hopes of fixing PPC bootstrap.

llvm-svn: 97040

necessary to swap the operands to handle NaN and negative zero properly.

Also, reintroduce logic for checking for NaN conditions when forming
SSE min and max instructions, fixed to take into consideration NaNs and
negative zeros. This allows forming min and max instructions in more
cases.

llvm-svn: 97025

to adding them in a determinstic order (bottom up from 
the root) based on the structure of the graph itself.

This updates tests for some random changes, interesting
bits: CodeGen/Blackfin/promote-logic.ll no longer crashes.
I have no idea why, but that's good right?

CodeGen/X86/2009-07-16-LoadFoldingBug.ll also fails, but
now compiles to have one fewer constant pool entry, making
the expected load that was being folded disappear.  Since it
is an unreduced mass of gnast, I just removed it.

This fixes PR6370

llvm-svn: 97023

llvm-svn: 97019

llvm-svn: 97011

creating a new node then replacing uses.

llvm-svn: 97000

llvm-svn: 96995

Previously, LiveIntervalAnalysis would infer phi joins by looking for multiply
defined registers. That doesn't work if the phi join is implicitly defined in
all but one of the predecessors.

llvm-svn: 96994

no id's would cause early exit allowing IsLegalToFold to return true
instead of false, producing a cyclic dag.

This was striking the new isel because it isn't using SelectNodeTo yet,
which theoretically is just an optimization.

llvm-svn: 96972

llvm-svn: 96971

segment.

llvm-svn: 96967

Speed up cycle checking significantly by caching results.

llvm-svn: 96956

llvm-svn: 96837

126.gcc nightly tests. These failures uncovered latent bugs that machine DCE
could remove one half of a stack adjust down/up pair, causing PEI to assert.
This update fixes that, and the tests now pass.

llvm-svn: 96822

llvm-svn: 96779

It turned out that we failed to emit proper symbol stubs on non-x86/darwin for ages (we emitted a reference to a stub, but no stub was emitted). The code inside x86-32/macho target objfile lowering should actually be the generic one - move it there.

This (I really, really hope) should fix EH issues on ppc/darwin
and arm/darwin.

llvm-svn: 96755