This patch represents Mips utilization of r186388 code that alows asm matcher to emit mnemonics contain '.' characters. This makes asm parser code simpler and more efficient.

llvm-svn: 186397

llvm-svn: 186274

llvm-svn: 186227

llvm-svn: 186222

llvm-svn: 186151

llvm-svn: 186000

llvm-svn: 185999

These exception-related opcodes are not used any longer.

llvm-svn: 185625

Use SmallVectorImpl::iterator/const_iterator instead of SmallVector to avoid specifying the vector size.

llvm-svn: 185606

Revert "Simplify landing pad lowering."
Revert "Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes."

llvm-svn: 185600

These exception-related opcodes are not used any longer.

llvm-svn: 185596

Use SmallVectorImpl::iterator/const_iterator instead of SmallVector to avoid specifying the vector size.

llvm-svn: 185540

floating point loads and stores.

No changes in functionality.

llvm-svn: 185399

have three register operands.

No intended functionality changes.

llvm-svn: 185376

Create a dedicated register class for floating point condition code registers and
move FCC0 from register class CCR to the new register class.

llvm-svn: 185373

function to lookup the proper tablegen'ed register enumeration.  Previously,
it was using the encoded value directly.

llvm-svn: 185026

llvm-svn: 185012

subs.

llvm-svn: 185011

 This patch introduces RegisterOperand class into Mips FPU instruction definitions and adds dedicated parser methods to MipsAsmParser. It is the first in a series of patches that should fix the problems with parsing Mips FPU instructions and optimize the code in MipsAsmParser.

llvm-svn: 184716

llvm-svn: 184642

llvm-svn: 184411

Access the TargetLoweringInfo from the TargetMachine object instead of caching it. The TLI may change between functions. No functionality change.

llvm-svn: 184360

The RenderMethod field in RegisterOperand class sets the name of the method on the target specific operand to call to add the target specific operand to an MCInst. This patch defines RenderMethod for mips RegisterOperand classes and removes redundant code from MipsAsmParser.cpp

llvm-svn: 184292

When producing objects that are abi compliant we are 
marking neither the object file nor the assembly file
correctly and thus generate warnings. 

We need to set the EF_CPIC flag in the ELF header when
generating direct object.

Note that the warning is only generated when compiling without PIC.

When compiling with clang the warning will be suppressed by supplying:

 -Wa,-mno-shared -Wa,-call_nonpic

Also the following directive should also be added:

	.option	pic0

when compiling without PIC,  This eliminates the need for supplying:

  -mno-shared -call_nonpic

on the assembler command line.

Patch by Douglas Gilmore

llvm-svn: 184220

Someone may want to do something crazy, like replace these objects if they
change or something.

No functionality change intended.

llvm-svn: 184175

Frame index handling is now target-agnostic, so delete the target hooks
for creation & asm printing of target-specific addressing in DBG_VALUEs
and any related functions.

llvm-svn: 184067

Backends shouldn't retain any global state. No functionality change.

llvm-svn: 183927

llvm-svn: 183804

The pass emits a call to sqrt that has attribute "read-none". This call will be
converted to an ISD::FSQRT node during DAG construction, which will turn into
a mips native sqrt instruction.
 

llvm-svn: 183802

No functionality changes.

llvm-svn: 183767

the Mips16 port. A few of the psuedos could either take signed
or unsigned arguments and I did not distinguish the case and improperly
rejected some valid cases that the assembler had previously accepted
when they were pure pseudos that expanded as assembly instructions.

llvm-svn: 183633

destination operands of an instruction.

No functionality changes.

llvm-svn: 183596

the internals of TargetMachine could change.

llvm-svn: 183493

Caching it as a pointer allows us to reset it if the TargetMachine object
changes.

llvm-svn: 183361

llvm-svn: 183334

Test commit for user vmedic, to verify commit access. One line of comment is added to MipsAsmParser.cpp.

llvm-svn: 183215

This also makes TableGen able to compute sizes/offsets of synthesized
indices representing tuples.

llvm-svn: 183061

Patch by Jyun-Yan You.

llvm-svn: 182984

Fixes PR16146: gdb.base__call-ar-st.exp fails after
pre-RA-sched=source fixes.

Patch by Xiaoyi Guo!

This also fixes an unsupported dbg.value test case. Codegen was
previously incorrect but the test was passing by luck.

llvm-svn: 182885

This patch solves the problem of numeric register values not being accepted:

../set_alias.s:1:11: error: expected valid expression after comma
        .set    r4,$4
                    ^
The parsing of .set directive is changed and handling of symbols in code 
as well to enable this feature. 

The test example is added.

Patch by Vladimir Medic

llvm-svn: 182807