PHI values may be deleted, causing the flags to be wrong. This fixes PR9616.

llvm-svn: 129092

And two test cases.

llvm-svn: 129090

llvm-svn: 129087

llvm-svn: 129081

llvm-svn: 129080

llvm-svn: 129079

llvm-svn: 129078

Prevent ARM DAG Combiner from doing an AND or OR combine on an illegal vector type (vectors of size 3). Also included test cases.

llvm-svn: 129074

tokenization to crash and burn.

llvm-svn: 129051

rdar://problem/9246844

llvm-svn: 129050

is equivalent to any other relevant value; it isn't true in general.
If it is equivalent, the LoopPromoter will tell the AST the equivalence.
Also, delete the PreheaderLoad if it is unused.

Chris, since you were the last one to make major changes here, can you check
that this is sane?

llvm-svn: 129049

The ARM disassembler was not recognizing USADA8 instruction.  Need to add checking for register values
for USAD8 and USADA8.

rdar://problem/9247060

llvm-svn: 129047

llvm-svn: 129045

llvm-svn: 129044

rdar://problem/9246650

llvm-svn: 129042

llvm-svn: 129041

llvm-svn: 129040

Teach the ARM peephole optimizer that RSB, RSC, ADC, and SBC can be used for folded comparisons, just like ADD and SUB.

llvm-svn: 129038

llvm-svn: 129036

llvm-svn: 129035

llvm-svn: 129034

The ARM disassembler should reject invalid (type, align) encodings as invalid instructions.

So, instead of:
Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30)
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
-------------------------------------------------------------------------------------------------
| 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 0: 0| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1|
-------------------------------------------------------------------------------------------------

	vst2.32	{d0, d2}, [r3, :256], r3

we now have:
Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30)
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
-------------------------------------------------------------------------------------------------
| 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 0: 0| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1|
-------------------------------------------------------------------------------------------------

mc-input.txt:1:1: warning: invalid instruction encoding
0xb3 0x9 0x3 0xf4
^

llvm-svn: 129033

llvm-svn: 129032

llvm-svn: 129030

Without any positive bias, there is nothing for the spill placer to to. It will
spill everywhere.

llvm-svn: 129029

Since these "Advanced SIMD and VFP" instructions have more specfic encoding bits
specified, if coproc == 10 or 11, we should reject the insn as invalid.

rdar://problem/9239922
rdar://problem/9239596

llvm-svn: 129027

llvm-svn: 129025

llvm-svn: 129024

If there are no positive nodes, the algorithm can be aborted early.

llvm-svn: 129021

This will allow us to abort the algorithm early if it is determined to be futile.

llvm-svn: 129020

Also set the encoding bits (for A8.6.303, A8.6.328, A8.6.329) Inst{3-0} = 0b0000,
in class NVLaneOp.

rdar://problem/9240648

llvm-svn: 129015

llvm-svn: 129012

Change the test to force a sign extension and expose the problem again.

llvm-svn: 129011

Keep track of llvm.dbg.value intrinsics with non null values.

llvm-svn: 129010

This takes the linking of libxul on linux from 6m54.931s to 5m39.840s.

llvm-svn: 129009

llvm-svn: 129002

DenseMap.

llvm-svn: 128994

llvm-svn: 128988

llvm-svn: 128986

About 90% of the relevant blocks are live-through without uses, and the only
information required about them is their number. This saves memory and enables
later optimizations that need to look at only the use-blocks.

llvm-svn: 128985