Select an OR with immediate as an ADD if the input bits are known zero. This allow the instruction to be 3address-fied if needed.

llvm-svn: 93152

Implement a feature (-vector-unaligned-mem) to allow targets to
ignore alignment requirements for SIMD memory operands.  This
is useful on architectures like the AMD 10h that do not trap on
unaligned references if a status bit is twiddled at startup time.

llvm-svn: 93151

Make InsertDbgValueIntrinsic() and get Offset take and recieve a uint64_t.
Get constness correct for getVariable() and getValue().

llvm-svn: 93149

good code on PR4216:

_test_bitfield:                                             ## @test_bitfield
	orl	$32962, %edi
	movl	$4294941946, %eax
	andq	%rdi, %rax
	ret

instead of:

_test_bitfield:
        movl    $4294941696, %ecx
        movl    %edi, %eax
        orl     $194, %edi
        orl     $32768, %eax
        andq    $250, %rdi
        andq    %rax, %rcx
        movq    %rdi, %rax
        orq     %rcx, %rax
        ret

Evan is looking into the remaining andq+imm -> andl optimization.

llvm-svn: 93147

BitsToClear case.  This allows it to promote expressions which have an
and/or/xor after the lshr, promoting cases like test2 (from PR4216) 
and test3 (random extample extracted from a spec benchmark).

clang now compiles the code in PR4216 into:

_test_bitfield:                                             ## @test_bitfield
	movl	%edi, %eax
	orl	$194, %eax
	movl	$4294902010, %ecx
	andq	%rax, %rcx
	orl	$32768, %edi
	andq	$39936, %rdi
	movq	%rdi, %rax
	orq	%rcx, %rax
	ret

instead of:

_test_bitfield:                                             ## @test_bitfield
	movl	%edi, %eax
	orl	$194, %eax
	movl	$4294902010, %ecx
	andq	%rax, %rcx
	shrl	$8, %edi
	orl	$128, %edi
	shlq	$8, %rdi
	andq	$39936, %rdi
	movq	%rdi, %rax
	orq	%rcx, %rax
	ret

which is still not great, but is progress.

llvm-svn: 93145

new BitsToClear result which allows us to start promoting
expressions that end with a lshr-by-constant.  This is
conservatively correct and better than what we had before
(see testcases) but still needs to be extended further.

llvm-svn: 93144

llvm-svn: 93143

the dest of the sext.

llvm-svn: 93128

the zext dest type.  This allows us to handle test52/53 in cast.ll,
and allows llvm-gcc to generate much better code for PR4216 in -m64
mode:

_test_bitfield:                                             ## @test_bitfield
	orl	$32962, %edi
	movl	%edi, %eax
	andl	$-25350, %eax
	ret

This also fixes a bug handling vector extends, ensuring that the
mask produced is a vector constant, not an integer constant.

llvm-svn: 93127

integer vectors as well as just integers.

llvm-svn: 93126

warning: suggest parentheses around ‘&&’ within ‘||’.
llvm-svn: 93121

simpler profitability predicate.

llvm-svn: 93111

llvm-svn: 93110

elimination of a sign extend to be a win, which simplifies 
the client of CanEvaluateSExtd, and allows us to eliminate
more casts (examples taken from real code).

llvm-svn: 93109

Document PFS argument to ParseValID() and ConvertGlobalOrMetadataValIDToValue().

llvm-svn: 93108

lshr+ashr instead of trunc+sext.  We want to avoid type 
conversions whenever possible, it is easier to codegen expressions
without truncates and extensions.

llvm-svn: 93107

llvm-svn: 93106

llvm-svn: 93105

bits known clear in the result and don't care about the # casts 
eliminated.  TD is also dead but keeping it for now.

llvm-svn: 93098

1) don't try to optimize a sext or zext that is only used by a trunc, let
   the trunc get optimized first.  This avoids some pointless effort in
   some common cases since instcombine scans down a block in the first pass.
2) Change the cost model for zext elimination to consider an 'and' cheaper
   than a zext.  This allows us to do it more aggressively, and for the next
   patch to simplify the code quite a bit.

llvm-svn: 93097

more expressions to be promoted and casts eliminated.

llvm-svn: 93096

llvm-svn: 93095

llvm-svn: 93093

llvm-svn: 93092

llvm-svn: 93091

commonIntCastTransforms into the callers, eliminating a switch,
and allowing the static predicate  methods to be moved down to
live next to the corresponding function.  No functionality 
change.

llvm-svn: 93089

"In order to ease automatic bindings generation, it would be helpful if boolean values were distinguishable from integers. The attached patch introduces "typedef int LLVMBool;", and uses LLVMBool instead of int throughout the C API, wherever a boolean value is called for."

Patch by James Y Knight!

llvm-svn: 93079

llvm-svn: 93067

R11, and then asserting that the target was in R9.  Since R9 isn't reserved for
the target anymore, and is used as an argument, this patch changes the
assertion.

llvm-svn: 93065

so that unnamed blocks are handled.

llvm-svn: 93059

Fixed linking of modules containing aliases to constant bitcasts.  Existing behaviour first tried to replace the aliases with the global that they aliased (rather than the bitcast), causing a crash on an assert because the types didn't match.  When this was fixed, it then did the same thing creating the new alias (creating an alias with a different type to its aliasee).  

Linking modules containing aliases to GEPs is still not quite right.  GEPs that are equivalent to bitcasts will be replaced by bitcasts, GEPs that are not will just break.  Aliases to GEPs that are not equivalent to bitcasts are horribly broken anyway (it might be worth adding an assert when creating the alias to prevent these being created; they just cause problems later).

llvm-svn: 93052

llvm-svn: 93046

base is the right expression type.  This fixes PR5981.

llvm-svn: 93045

really does need to be a vector type, because
TargetLowering::getOperationAction for SIGN_EXTEND_INREG uses that type,
and it needs to be able to distinguish between vectors and scalars.

Also, fix some more issues with legalization of vector casts.

llvm-svn: 93043

llvm-svn: 93042

Disable  copy ctor and operator= for NamedMDSymTable. Hide typedef that should be public.

llvm-svn: 93041

llvm-svn: 93039

llvm-svn: 93038

llvm-svn: 93037

llvm-svn: 93032