llvm-svn: 9317

llvm-svn: 9316

Header files will be on the way.

llvm-svn: 9298

Update the sparc backend to at least compile correctly with the new varargs stuff even if it's not all implemented yet.

llvm-svn: 9223

llvm-svn: 8687

generate the appropriate CallArgsDescriptor and tmp. virtual regs.

llvm-svn: 8554

llvm-svn: 7951

All non-FP cases use LDXi as before.

llvm-svn: 7765

llvm-svn: 7734

* setjmp() simply returns 0
* longjmp() simply calls abort()

llvm-svn: 7676

use or def-and-use operands can be substituted after one def-only
operand has been substituted.

llvm-svn: 7674

2. Handle fp-to-uint conversions directly here instead of relying on
   a pre-transformation to replace them with the 2-step conversion.
3. Use size rather than explicitly checking types when deciding what
   opcodes to use, wherever possible.  This is less error prone (the
   bug fix above was not the first time!).
4. Float-to-pointer casts shd now work though this hasn't been tested.

llvm-svn: 7645

llvm-svn: 7603

than machine register size), not just the second operand.

llvm-svn: 7475

in ConvertConstantToIntType.

llvm-svn: 7395

   causing a nasty array bound error later.
2. Fix silly typo causing logical shift of unsigned long to use
   SRL instead of SRLX.

llvm-svn: 7330

(1) Cannot use ANDN(ot), ORN, and XORN for boolean ops, only bitwise ops.

(2) Conditional move instructions must distinguish signed and unsigned
    condition codes, e.g., MOVLE vs. MOVLEU.

(3) Conditional-move-on-register was using the cond-move-on-cc opcodes,
    which produces a valid-looking instruction with bogus registers!

(4) Here's a really cute one: dividing-by-2^k for negative numbers needs to
    add 2^k-1 before shifting, not add 1 after shifting.  Sadly, these
    are the same when k=0 so our poor test case worked fine.

(5) Casting between signed and unsigned values was not correct:
    completely reimplemented.

(6) Zero-extension on unsigned values was bogus: I was only doing the
    SRL and not the SLLX before it.  Don't know WHAT I was thinking!

(7) And the most important class of changes: Sign-extensions on signed values.
    Signed values are not sign-extended after ordinary operations,
    so they must be sign-extended before the following cases:
	-- passing to an external or unknown function
	-- returning from a function
	-- using as operand 2 of DIV or REM
	-- using as either operand of condition-code setting operation
           (currently only SUBCC), with smaller than 32-bit operands


Also, a couple of improvements:

(1) Fold cast-to-bool into Not(bool).  Need to do this for And, Or, XOR also.

(2) Convert SetCC-Const into a conditional-move-on-register (case 41)
    if the constant is 0.  This was only being done for branch-on-SetCC-Const
    when the branch is folded with the SetCC-Const.

llvm-svn: 7159

integer overflow):
We need to use %icc and not %xcc for comparisons on 32-bit or smaller
integer values.

llvm-svn: 7111

area to avoid using up precious stack space within the 4095 offset limit
from %fp.  Such objects that would themselves live at a large offset
were being put there already so this is a simple change.

llvm-svn: 7066

(1) select: Ok to convert a pointer to a float or double.
(2) regalloc: Some MachineInstr* for caller-saving code before a call
    were being inserted before and after the call!
(3) Don't insert the caller-saving instructions in the
    MachineCodeForInstruction for the Call instruction.
    *All* instructions generated by register allocation need to be
    recorded in those maps, but it needs to be done uniformly.

llvm-svn: 7051

llvm-svn: 6859

* BPA and BPN do not take a %cc register as a parameter
* SLL/SRL/SRA{r,i}5 are there for a reason - they are ONLY 32-bit instructions
* Likewise, SLL/SRL/SRAX{r,i}6 are only 64-bit
* Added WRCCR{r,i} opcodes

llvm-svn: 6655

* Stop code from wrapping to the next line.

llvm-svn: 6566

SparcInstrSelection.cpp:
* Fixed opcodes to return correct 'i' version since the two functions are each
  only used in one place.
* Changed name of function to have an 'i' in the name to signify that they each
  return an immediate form of the opcode.
* Added a warning if either of the functions is ever used in a context which
  requires a register-version opcode.

SparcV9_F4.td: fixed class F4_3, added F4_4 and notes that F4_{1,2} need fixing
SparcV9.td: added the MOV(F)cc instructions

llvm-svn: 6548

call arguments and return values:
Now all copy operations before and after a call are generated during
selection instead of during register allocation.
The values are copied to virtual registers (or to the stack), but
in the former case these operands are marked with the correct physical
registers according to the calling convention.
Although this complicates scheduling and does not work well with
live range analysis, it simplifies the machine-dependent part of
register allocation.

llvm-svn: 6465

llvm-svn: 6464

llvm-svn: 6459

Code beautification for the rest of the code: changed layout to match the rest
of the code base.

llvm-svn: 6446

Here I had to make one non-trivial change: add a function to get a version of
the opcode that takes an immediate, given an opcode that takes all registers.

This is required because sometimes it is not known at construction time which
opcode is used because opcodes are passed around between functions.

llvm-svn: 6375

Fixed spilling of %fcc[0-3] which are part of %fsr.
Moved some machine-independent reg-class code to class TargetRegInfo
from SparcReg{Class,}Info.

llvm-svn: 6339

negative values.  Need to add one to a negative value before right shift!

llvm-svn: 6334

llvm-svn: 6325

consistent with the style of LLVM's code base (and itself! it's inconsistent in
some places.)

No functional changes were made.

llvm-svn: 6265

Eliminated `using' directives.

llvm-svn: 6261

llvm-svn: 6249

llvm-svn: 5961

llvm-svn: 5932

llvm-svn: 5317

llvm-svn: 5299

llvm-svn: 5294