llvm-svn: 9309

llvm-svn: 9289

llvm-svn: 9202

Update names of some pass creator fns in addPassesToEmitAssembly().
FunctionInfo is gone.

llvm-svn: 8599

llvm-svn: 8311

llvm-svn: 8306

 addPassesToEmitMachineCode now both take a FunctionPassManager.
Factory methods for function passes now return type FunctionPass *.

llvm-svn: 7835

llvm-svn: 7802

that depends on machine register size.
Moved insertCallerSavingCode() to PhyRegAlloc and
moved isRegVolatile and modifiedByCall to TargetRegInfo: they are all
machine independent.  Remove several dead functions.

llvm-svn: 7392

    Single and FP double reg types (which share the same reg class).
    Now all methods marking/finding unused regs consider the regType
    within the reg class, and SparcFloatRegClass specializes this code.
(2) Remove machine-specific regalloc. methods that are no longer needed.
    In particular, arguments and return value from a call do not need
    machine-specific code for allocation.
(3) Rename TargetRegInfo::getRegType variants to avoid unintentional
    overloading when an include file is omitted.

llvm-svn: 7334

llvm-svn: 7208

llvm-svn: 7114

llvm-svn: 7109

system.

llvm-svn: 7014

llvm-svn: 6711

call arguments and return values:
Now all copy operations before and after a call are generated during
selection instead of during register allocation.
The values are copied to virtual registers (or to the stack), but
in the former case these operands are marked with the correct physical
registers according to the calling convention.
Although this complicates scheduling and does not work well with
live range analysis, it simplifies the machine-dependent part of
register allocation.

llvm-svn: 6465

For one, converting register numbers based on class in the code emitter.

llvm-svn: 6447

changed.

llvm-svn: 6380

Also, added annotations to how instructions are modified (reg/imm operands).
Added prototype for adding register numbers to values pass for interfacing with
the target-independent register allocators in the JIT.

llvm-svn: 6366

Fixed spilling of %fcc[0-3] which are part of %fsr.
Moved some machine-independent reg-class code to class TargetRegInfo
from SparcReg{Class,}Info.

llvm-svn: 6339

llvm-svn: 6325

llvm-svn: 6323

llvm-svn: 6320

llvm-svn: 6249

llvm-svn: 5317

Eliminate dependency on RegClass.h

llvm-svn: 5315

llvm-svn: 5272

llvm-svn: 5204

Rename MachineOptInfo to TargetoptInfo
Rename MachineCacheInfo to TargetCacheInfo

llvm-svn: 5202

llvm-svn: 5199

* Move some sparc specific code here from Target files

llvm-svn: 5176

llvm-svn: 4420

llvm-svn: 4415

llvm-svn: 4372

llvm-svn: 4359

really is sparc specific.

llvm-svn: 4308

llvm-svn: 4301

llvm-svn: 4129

needs the RegClass list to be passed in.

llvm-svn: 3964

llvm-svn: 3960