Header files will be on the way.

llvm-svn: 9298

llvm-svn: 9027

llvm-svn: 8299

llvm-svn: 8297

llvm-svn: 8293

llvm-svn: 8292

immed. field.  Moved insertCallerSavingCode() to PhyRegAlloc: it is
now machine independent.  Remove all uses of PhyRegAlloc.

llvm-svn: 7391

    Single and FP double reg types (which share the same reg class).
    Now all methods marking/finding unused regs consider the regType
    within the reg class, and SparcFloatRegClass specializes this code.
(2) Remove machine-specific regalloc. methods that are no longer needed.
    In particular, arguments and return value from a call do not need
    machine-specific code for allocation.
(3) Rename TargetRegInfo::getRegType variants to avoid unintentional
    overloading when an include file is omitted.

llvm-svn: 7334

llvm-svn: 7217

llvm-svn: 7208

(1) An int CC live range must be spilled if there are any interferences,
    even if no other "neighbour" in the interf. graph has been allocated
    that reg. yet.  This is actually true of any class with only one reg!

(2) SparcIntCCRegClass::colorIGNode sets the color even if the LR must
    be spilled so that the machine-independent spill code doesn't have to
    make the machine-dependent decision of which CC name to use based on
    operand type: %xcc or %icc.  (These are two halves of the same register.)

(3) LR->isMarkedForSpill() is no longer the same as LR->hasColor().
    These should never have been the same, and this is necessary now for #2.

(4) All RDCCR and WRCCR instructions are directly generated with the
    phony number for %ccr so that EmitAssembly/EmitBinary doesn't have to
    deal with this.

llvm-svn: 7151

integer overflow):
We need to use %icc and not %xcc for comparisons on 32-bit or smaller
integer values.

llvm-svn: 7111

(1) select: Ok to convert a pointer to a float or double.
(2) regalloc: Some MachineInstr* for caller-saving code before a call
    were being inserted before and after the call!
(3) Don't insert the caller-saving instructions in the
    MachineCodeForInstruction for the Call instruction.
    *All* instructions generated by register allocation need to be
    recorded in those maps, but it needs to be done uniformly.

llvm-svn: 7051

llvm-svn: 6692

* BPA and BPN do not take a %cc register as a parameter
* SLL/SRL/SRA{r,i}5 are there for a reason - they are ONLY 32-bit instructions
* Likewise, SLL/SRL/SRAX{r,i}6 are only 64-bit
* Added WRCCR{r,i} opcodes

llvm-svn: 6655

llvm-svn: 6503

call arguments and return values:
Now all copy operations before and after a call are generated during
selection instead of during register allocation.
The values are copied to virtual registers (or to the stack), but
in the former case these operands are marked with the correct physical
registers according to the calling convention.
Although this complicates scheduling and does not work well with
live range analysis, it simplifies the machine-dependent part of
register allocation.

llvm-svn: 6465

llvm-svn: 6377

Fixed spilling of %fcc[0-3] which are part of %fsr.
Moved some machine-independent reg-class code to class TargetRegInfo
from SparcReg{Class,}Info.

llvm-svn: 6339

Eliminated `using' directives.

llvm-svn: 6261

llvm-svn: 6249

llvm-svn: 6145

llvm-svn: 5316

Eliminate dependency on RegClass.h

llvm-svn: 5315

llvm-svn: 5307

llvm-svn: 5305

llvm-svn: 5303

llvm-svn: 5291

llvm-svn: 5284

llvm-svn: 5204

* Constant pool and frame info is no longer directly in MachineFunction

llvm-svn: 5177

llvm-svn: 4408

llvm-svn: 4354

llvm-svn: 4347

llvm-svn: 4345

llvm-svn: 4331

llvm-svn: 4301

    overhead: Merge 3 parallel vectors into 1, change regsUsed hash_set to be a
    bitvector.  Sped up LLC a little less than 10% in a debug build!

llvm-svn: 4261

llvm-svn: 4170

llvm-svn: 4128