Header files will be on the way.

llvm-svn: 9298

llvm-svn: 9295

llvm-svn: 9288

Make insertFarJumpAtAddr() return void, because nothing uses its return value.
Remove some commented-out code.
Implement replaceMachineCodeForFunction() for SPARC.

llvm-svn: 9203

jello statistic for this (just divide #-bytes-of-code-emitted by 4).

Rewrite head-of-file comment.

llvm-svn: 9098

llvm-svn: 9027

llvm-svn: 8772

* Generate a single BA instead of 6-instruction JUMP if possible
  (this occurs both in the creation and overwriting of the stub code)
* If possible, rewrite the ORIGINAL call to call the generated function
  directly, thus bypassing the stub entirely

Also added some statistics on how often calls are overwritten and how often the
CompilationCallback is invoked.

llvm-svn: 8376

* Break apart saving and restoring registers into separate functions
* Instead of saving single and double FP registers, just save the double
  registers -- aliasing helps preserve the single FP registers as well.
* Request just as much memory for a stub as we actually use

llvm-svn: 8200

rounding up to a page, we need to request (num instrs * 4) bytes. However, I
think that 64 bytes is overkill for the stub function.

llvm-svn: 7888

llvm-svn: 7884

  registers are global, are NOT windowed, and hence can be clobbered!
* Removed unused register shorthand notations
* Fixed and cleaned up comments in inline assembly

llvm-svn: 7853

 addPassesToEmitMachineCode now both take a FunctionPassManager.

llvm-svn: 7837

because saving i1 and i2 to their ``designated'' stack slots corrupts unknown
memory in other functions, standard libraries, and worse.

In addition, this has the benefit of improving JIT performance because we
eliminate writing out 4 instructions in CompilationCallback() and 2 loads and 2
stores.

llvm-svn: 7653

* Doxygen-ified comments
* Added capability to make far calls (i.e., beyond 30 bits in CALL instr)
  which implies that we need to delete function references that were added by
  the call to addFunctionReference() because the actual call instruction is 10
  instructions away (thanks to 64-bit address construction)
* Cleaned up code that generates far jumps by using an array+loop

SparcV9CodeEmitter.h:
* Explained more of the side-effects of emitFarCall()

llvm-svn: 7639

llvm-svn: 7495

  instead of assert()ing
* Fixed a nasty bug where '07' was used instead of register 'o7'

llvm-svn: 7382

llvm-svn: 7343

now works in instructions which require a 2-bit or 3-bit INTcc code.

Incidentally, that means that the representation of INTcc registers is now the
same in both integer and FP instructions. Thus, code became much simpler and
cleaner.

llvm-svn: 7185

allow, i.e. make a sequence of instructions to enable an indirect call using
jump-and-link and 2 temporary registers (which we save and ultimately restore).

Warning: if the delay slot of a function call is used to do meaningful work and
not just a NOP, this behavior is incorrect. However, the Sparc backend does not
yet utilize the delay slots effectively, so it is not necessary to make an
overly complicated algorithm for something that's not used.

llvm-svn: 7178

* FP double registers are now coded correctly
* Removed function which converted registers based on register types, it was
  broken (because regTypes are broken)

llvm-svn: 7175

correct: empirically, "regType" is wrong for a number of registers. Thus, one
can only rely on the "regClass" to figure out what kind of register one is
dealing with.

This change switches to using only "regClass" and adds a few extra DEBUG() print
statements and a few clean-ups in comments and code, mostly minor.

llvm-svn: 7103

llvm-svn: 6657

address of a floating-point (allocated via ConstantPool) correctly.

llvm-svn: 6647

* Do not block a print statement with a DEBUG() guard if we're going to abort()

llvm-svn: 6645

that tests can automatically diff the output.

llvm-svn: 6642

Now %fcc registers are recognized correctly.

llvm-svn: 6640

llvm-svn: 6633

  in Emitter.cpp, just convert the Sparc version of the constant pool into
  what's already supported and inter-operate.
* Implemented a first pass at lazy function resolution in the JITResolver. That
  required adding a SparcV9CodeEmitter pointer to simplify generating
  bit-patterns of the instructions.
* SparcV9CodeEmitter now creates and destroys static TheJITResolver, which makes
  sense because the SparcV9CodeEmitter is the only user of TheJITResolver, and
  lives for the entire duration of the JIT (via PassManager which lives in VM).
* Changed all return values in the JITResolver to uint64_t because of the 64-bit
  Sparc architecture.
* Added a new version of getting the value of a GlobalValue in the
  SparcV9CodeEmitter, which now works for already-generated functions (JITted or
  library functions).
* Removed little-used and unused functions, cleaning up the internal view of the
  SparcV9CodeEmitter.

llvm-svn: 6612

llvm-svn: 6568

llvm-svn: 6536

from lib/Target/X86/X86CodeEmitter.cpp .

llvm-svn: 6530

llvm-svn: 6522

llvm-svn: 6462

* ability to save BasicBlock references to be resolved later
* register remappings from the enum values to the real hardware numbers

llvm-svn: 6449

llvm-svn: 6381

MachineInstr can later be patched up correctly.

llvm-svn: 6378

MachineCodeEmitter to make a pass-through debugger -- output to memory and to
std::cerr.

llvm-svn: 6363

that assembles instructions is generated via TableGen (and hence must be built
before building this directory, but that's already the case in the top-level
Makefile).

Also added is .cvsignore to ignore the generated file `SparcV9CodeEmitter.inc',
which is included by SparcV9CodeEmitter.cpp .

llvm-svn: 6357